Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 1, 2006, Pages 179-196

  Pham, D C ^a   Aipperspach, T ^a   Boerstler, D ^a   Bolliger, M ^a   Chaudhry, R ^a   Cox, D ^a   Harvey, P ^a   Harvey, P M ^a   Hofstee, H P ^a   Johns, C ^a   Kahle, J ^a   Kameyama, A ^a   Keaty, J ^a   Masubuchi, Y ^a   Pham, M ^a   Pille, J ^a   Posluszny, S ^a   Riley, M ^a   Stasiak, D L ^a   Suzuoki, M ^a   Takahashi, O ^a   Warnock, J ^a   Weitzel, S ^a   Wendel, D ^a   Yazawa, K ^a   more..

^a IBM   (United States)

Author keywords

64 bit; 90 nm; Circuit complexity; Custom circuit design; First generation cell processor; Flexible IO interface; Memory interface controller; Multi core SoC; Multiple synergistic processors; Power architecture processor; SOI technology

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CIRCUIT THEORY; COMPUTER OPERATING SYSTEMS; POWER AMPLIFIERS; POWER GENERATION; RECTIFYING CIRCUITS;

64 BIT; 90 NM; CIRCUIT COMPLEXITY; CUSTOM CIRCUIT DESIGN; FIRST-GENERATION CELL PROCESSOR; FLEXIBLE IO INTERFACE; MEMORY INTERFACE CONTROLLER; MULTI-CORE SOC; MULTIPLE SYNERGISTIC PROCESSORS; SOI TECHNOLOGY;

ELECTRIC NETWORK ANALYSIS;

EID: 31344457004     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.859896     Document Type: Article

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