40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Kanda, Kouichi ^a   Yamazaki, Daisuke ^a   Yamamoto, Takuji ^a   Horinaka, Minoru ^a   Ogawa, Junji ^a   Tamura, Hirotaka ^a   Onodera, Hiroyuki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144454462     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. D. Kehrer et al., "40Gb/s 2:1 Multiplexer and 1:2 Demultiplexer in 120nm CMOS," ISSCC Dig. Tech. Papers, pp. 344-345, Feb., 2003.
2. A. Rylyakov et al., "A 30Gb/s 1:4 Demultiplexer in 0.12μm CMOS," ISSCC Dig. Tech.. Papers, pp. 176-177, Feb., 2003.
3. D. Yamazaki et al., "A25GHz Clock Buffer and a 50Gb/s 2:1 Selector in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 240-241, Feb., 2004.
4. T. Yamamoto et al., "A 43Gb/s 2:1 Selector IC in 90nm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 238-239, Feb., 2004.
5. S. Galal and B. Razavi, "40Gb/s Amplifier and ESD Protection Circuit in 0.18μm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 480-481, Feb., 2004.