Analyzing on-chip communication in a MPSoC environment

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 752-757

  Loghi, Mirko ^a   Angiolini, Federico ^b   Bertozzi, Davide ^b   Benini, Luca ^b   Zafalon, Roberte ^c  

^a UNIVERSITY OF VERONA   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION INFRASTRUCTURE; EXTERNAL MEMORY LATENCY; INTERCONNECTION ARCHITECTURE; MULTIPROCESSOR SYSTEMS-ON-CHIPS (MPSOC); ARCHITECTURAL MISMATCHES; COMMUNICATION ARCHITECTURES; COMPARATIVE ANALYSIS; MULTIPROCESSOR-SYSTEM; ON CHIP COMMUNICATION; SIMULATION ENVIRONMENT; SYSTEM CONFIGURATIONS;

BUFFER STORAGE; COMMUNICATION; COMPUTER SIMULATION; INTERCONNECTION NETWORKS; MIDDLEWARE; SIGNAL PROCESSING; STANDARDS; SYNCHRONIZATION; TELECOMMUNICATION TRAFFIC; EXHIBITIONS; MULTIPROCESSING SYSTEMS;

MULTIPROCESSING SYSTEMS; ARM PROCESSORS;

EID: 3042511814     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268966     Document Type: Conference Paper

References (16)

1. L. Benini and G. Micheli. Networks on chips: a new soc paradigm. IEEE Computer, 35(1):70-78, January 2002.
2. A. Brinkmann, J. Niemann, I. Hehemann, D. Langen, M. Porrmann, and U. Ruckert. On-chip interconnects for next generation systems-on-chips. IEEE ASIC/SOC Conf., pages 212-215, September 2002.
3. M. Gasteier and M. Glesner. Bus-based communication synthesis. ACM Tran. Des. Autom. Electron. Syst., pages 1-11, January 1999.
4. K. Hines and G. Borriello. Optimizing communication in embedded system cosimulation. Int. Workshop on Hardware/Software Codesign, pages 121-125, 1997.
5. M. Kreutz, L. Carro, A. Zeferino, and A. Susin. Communication architectures for systems-on-chip. Symposium on Integrated Circuits an Systems Design, pages 14-19, September 2001.
6. K. Lahiri, A. Raghunathan, and S. Dey. Evaluation of the traffic performance characteristics of system-on-chip communication architectures, 2001.
7. K. Lahiri, A. Raghunathan, and S. Dey. System-level performance analysis for designing on-chip communication architectures. IEEE Trans. On CAD of Ics and Systems, 20(6):768-783, June 2001.
8. V. Lahtinen, E. Salminen, K. Kuusilinna, and T. Hamalainen. Comparison of synthesized bus and crossbar interconnection architectures. ISCAS, pages V433-V436, May 2003.
9. J. Rowson and A. Sangiovanni-Vincentelli. Interface based design. DAC, pages 178-183, June 1997.
10. RTEMS home page, http://www.rtems.com.
11. K. K. Ryu, E. Shin, and V. J. Mooney. A comparison of five different multiprocessor soc bus architectures. EUROMICRO. pages 202-209, September 2001.
12. Software ARM, http://www.g141.com/projects/swarm/.
13. S. M. Xinping Zhu. A hierarchical modeling framework for on-chip communication architectures. In Proceedings of International Conference on Computer-Aided Design 2002, November 2002.
14. T. Yen and W. Wolf. Communication synthesis for distributed embedded systems. Int. Conf. On CAD, pages 288-294, November 1995.
15. C. A. Zeferino, M. E. Kreutz, L. Carro, and A. A. Susin, A study on communication issues for systems-on-chip. SBCCI, pages 121-126, September 2002.
16. Y. Zhang and M. Irwin. Power and performance comparison of crossbars and buses as on-chip interconnect structures. Asilomar Conference on Signals, Systems and Computers, 1:378-383, October 1999.