Narrow bus encoding for low-power DSP systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 5, 2001, Pages 656-660

  Shin, Youngsoo ^a   Choi, Kiyoung ^b   Chang, Young Hoon ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Seoul National University   (South Korea)

^c Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

CMOS; Low power; Switching activity; System level

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

DATA BUSES;

DIGITAL SIGNAL PROCESSING;

EID: 0035472993     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.953499     Document Type: Article

References (13)

1. Power consumption estimation in CMOS VLSI chips
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6. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
7. System-level power optimization of special purpose applications: The beach solution
8. Partial bus-invert coding for power optimization of system level bus
9. Fast prototyping of datapath-intensive architectures
10. A parser processor for MPEG-2 audio and AC-3 decoding
11. A digital signal processor for low power