SCOPUS 정보 검색 플랫폼

Volumn 1, Issue 4, 1986, Pages 187-196

The torus routing chip

(2) Dally, William J a Seitz, Charles L a

a CALIFORNIA INSTITUTE OF TECHNOLOGY (United States)

Author keywords

Asynchronous logic; Communication networks; Concurrent computation; Deadlock free routing; Interconnection networks; Message passing multiprocessers; Parallel processing; Self timed logic; VLSI

Indexed keywords

INTEGRATED CIRCUITS, VLSI - APPLICATIONS;

COMMUNICATION NETWORKS; INTERCONNECTION NETWORKS; MESSAGE-PASSING MULTIPROCESSERS; PARALLEL PROCESSING; TORUS ROUTING CHIP;

COMPUTER SYSTEMS, DIGITAL;

EID: 0022920181 PISSN: 01782770 EISSN: 14320452 Source Type: Journal
DOI: 10.1007/BF01660031 Document Type: Article

Times cited : (495)

References (17)

1
- 84936605818
- Bryant R, Schuster M, Whiting D (1983) MOSSIM II: A Switch-Level Simulator for MOS LSI User's manual Caltech Tech Rep 5033: TR: 82 (January)

2
- 84936605820
- Dally WJ, Seitz CL (1986) Deadlock-free message routing in multiprocessor interconnection networks. Dept Comput Sci, California Institute of Technology, Tech Rep 5206: TR:86

3
- 84936605830
- Dally WJ: CNTK: An embedded language for circuit description. Dept Comput Sci, California Institute of Technology, Display File (in preparation)

4
- 0022102734
- Synchronizing large VLSI Processor arrays
- (1985) IEEE Trans Comp, C , vol.34 , Issue.8 , pp. 734-740
- Fisher, A.L.¹ Kung, H.T.²

5
- 0019556656
- Prevention of deadlocks in packetswitched data transport systems
- (1981) IEEE Transactions on Communications , vol.29 , Issue.4 , pp. 512-524
- Gunther, K.D.¹

6
- 84936605833
- Intel iPSC User's Guide (1985) Intel Document No. 175455-001 (August)

7
- 0018518295
- Virtual, cut-through: a new computer communication switching technique
- (1979) Comput Networks , vol.3 , pp. 267-286
- Kermani, P.¹ Kleinrock, L.²

8
- 0003821875
- Wiley, New York
- (1976) Queuing systems; vol 2 , pp. 438-440
- Kleinrock, L.¹

9
- 84936605827
- Lang CR (1982) The extension of object-oriented languages to a homogeneous concurrent architecture. Dept. of Computer Science, California Institute of Technology, Technical Report, 5014: TR:82 118–124

10
- 0022011363
- The magic VLSI layout system
- (1985) IEEE Design and Test of Computers , vol.2 , Issue.1 , pp. 19-30
- Ousterhout, J.K.¹

11
- 0001951703
- System Timing
- C.A., Mead, L.A., Conway, Addison Wesley, London Amsterdam Paris
- (1980) Introduction to VLSI Systems
- Seitz, C.L.¹

12
- 0021604998
- Concurrent VLSI Architectures
- (1984) IEEE Trans Comput, C , vol.33 , Issue.12 , pp. 1247-1265
- Seitz, C.L.¹

13
- 0021793126
- The cosmic cube
- (1985) CACM , vol.28 , Issue.1 , pp. 22-33
- Seitz, C.L.¹

14
- 84936605829
- Seitz CL et al. (1985) The Hypercube Commun Chip. Dept. of Computer Science, California Institute of Technology, Display Fiel 5182: DF:85

15
- 84936605918
- Steele CS (1985) Placement of communicating processes on multiprocessor networks. Dept Comput Sci, California Institute of Technology, Tech Rep 5184:TR:85.

16
- 84936561435
- Prentice Hall, Englwood Cliffs, NJ
- (1981) Comput networks , pp. 15-21
- Tanenbaum, A.S.¹

17
- 84936605916
- Trotter D (1985) Miss MOSIS, Scalable CMOS Rules, Version 1.2

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.