Next generation CoreConnect™ processor local bus architecture

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 221-225

  Hofmann, Rick ^a   Drerup, Ben ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

Index Terms Computer Architecture; Multiprocessing; On Chip Bus; Systems On a Chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUSES; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; WIRELESS TELECOMMUNICATION SYSTEMS;

EMBEDDED APPLICATION; INDEX TERMS; MULTIPLE PROCESSORS; MULTIPROCESSING; ON-CHIP BUS; PERVASIVE APPLICATIONS; SYSTEMS-ON-A CHIPS; WIRED AND WIRELESS COMMUNICATIONS;

SYSTEM-ON-CHIP;

EID: 84949464840     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158060     Document Type: Conference Paper

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