Analysis and implementation of practical, cost-effective networks on chips

IEEE Design and Test of Computers

Volumn 22, Issue 5, 2005, Pages 422-433

  Lee, Se Joong ^a   Lee, Kangmin ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DATA COMMUNICATION SYSTEMS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; SYNCHRONIZATION;

BURST PACKET TRANSMISSION; MESOCHRONOUS COMMUNICATION; NETWORKS ON CHIPS;

INTEGRATED CIRCUIT LAYOUT;

EID: 27344452711     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.103     Document Type: Article

References (16)

1. D. Pham et al., "The Design and Implementation of a First-Generation CELL Processor," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press, 2005, pp. 184-185.
2. S. Torii et al., "A 600MIPS 120mW 70 μA Leakage Triple-CPU Mobile Application Processor Chip," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press, 2005, pp. 136-137.
3. M. Taylor et al. "A 16-Issue Multiple-Program Counter Microprocessor with Point-to-Point Scalar Operand Network," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 03), IEEE Press, 2003, pp. 170-171.
4. W.J. Dally et al., "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 684-689.
5. S.-J. Lee et al., "Packet-Switched On-Chip Interconnection Network for System-on-Chip Applications," IEEE Trans. Circuits and Systems Part II, vol. 52, no. 6, June 2005, pp. 308-312.
6. S. Murali et al., "SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs," Proc. Design Automation Conf. (DAC 04), ACM Press, 2004, pp. 914-919.
7. H. Jingcao et al., "DyAD - Smart Routing for Networks-on-Chip," Proc. Design Automation Conf. (DAC 04), ACM Press, 2004, pp. 260-263.
8. E. Rijpkema et al., "Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip," Proc. Design, Automation and Test in Europe (DATE 03), IEEE CS Press, 2003, pp. 350-355.
9. D. Bertozzi et al., "Xpipes: A Network-on-Chip Architecture for Gigascale System-on-Chip," IEEE Circuits and Systems Magazine, vol. 4, no. 2, 2004, pp. 18-31.
10. S.-J. Lee et al., "An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip," Proc. IEEE Int'l Solid. State Circuits Conf. (ISSCC 03), IEEE Press, 2003, pp. 468-469.
11. K. Lee et al., "A 51mW 1.6GHZ On-Chip Network for Low Power Heterogeneous SoC Platform," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 04), IEEE Press, 2004, pp. 152-153.
12. S.-J. Lee et al., "Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme," Proc. Symp. VLSI Circuits, IEEE Press, 2005, pp. 104-107.
13. K. Lee et al., "SILENT: Serialized Low Energy Transmission Coding for On-Chip Interconnection Networks," Proc. Int'l Conf. Computer-Aided Design (ICCAD 04), 2004; http://www.iccad.com/ archive.html.
14. K. Kim et al., "An Arbitration Look-Ahead Scheme for Reducing End-to-End Latency in Networks on Chip," Proc. Int'l Symp. Circuits and Systems (ISCAS 05), IEEE Press, 2005, pp. 2357-2360.
15. H.-S. Wang et al., "A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers," IEEE Micro, vol. 23, no. 1, Jan.-Feb. 2003, pp. 26-35.
16. M. Millberg et al., "The Nostrum Backbone - A Communication Protocol Stack for Networks on Chip," Proc. 17th Int'l Conf. VLSI Design, IEEE CS Press, 2004, pp. 693-696.