NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

IEEE Transactions on Parallel and Distributed Systems

Volumn 16, Issue 2, 2005, Pages 113-129

  Bertozzi, Davide ^a   Jalabert, Antoine ^b   Murali, Srinivasan ^c   Tamhankar, Rutuparna ^c   Stergiou, Stergios ^c   Benini, Luca ^a   De Micheli, Giovanni ^c  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b CEA LETI   (France)

^c Stanford University   (United States)

Author keywords

Architecture; Mapping; Networks on chip; Synthesis; Systems on chip

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; CONSUMER ELECTRONICS; DIGITAL SIGNAL PROCESSING; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; OPTIMIZATION;

MAPPING ALGORITHMS; NETWORKS-ON-CHIP; SYSTEMS-ON-CHIP;

MULTIPROCESSING SYSTEMS;

EID: 14844365666     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2005.22     Document Type: Article

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