System-level design: Orthogonalization of concerns and platform-based design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 12, 2000, Pages 1523-1543

  Keutzer, Kurt ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Design automation; Design methodology; Digital systems; Multiprocessor interconnection

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; EMBEDDED SYSTEMS; INTERCONNECTION NETWORKS; MULTIPROCESSING SYSTEMS; PROGRAM COMPILERS;

ELECTRONIC DESIGN AUTOMATION (EDA);

INTEGRATED CIRCUIT LAYOUT;

EID: 0034428118     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.898830     Document Type: Article

References (35)

1. M. Pinto, "Feature System Design," unpublished, June 1999.
2. Giga Scale Research Center [Online] . Available: http://www.gigascale.org
3. F. Balarin et al., Hardware-Software Co-Design of Embedded Systems: The POLIS Approach. Norwell, MA: Kluwer., 1998.
4. J. Rowson and A. Sangiovanni-Vincentelli, "System level design," EE Times, 1996.
5. "Interface-based design," in Proc. 34th Design Automation Conf. (DAC-97), Las Vegas, NV, June 1997, pp. 178-183.
6. C. Szyperski, Component Software: Beyond Object-Oriented Software. Reading, MA: ACM/Addison-Wesley, 1998.
7. A. Sangiovanni-Vincentelli, R. McGeer, and A. Saldanha, "Verification of integrated circuits and systems," presented at the 1996 Design Automation Conf., Las Vegas, NV, June 1996.
8. E. Lee and A. Sangiovanni-Vincentelli, "A unified framework for comparing models of computation," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1217-1229, Dec. 1998.
9. M. Sgroi, L. Lavagno, and A. Sangiovanni-Vincentelli, Formal models for embedded system design, in IEEE Design Test Comput. (Special Issue on System Design), 2000. to appear in.
10. J. L. da Suva Jr., M. Sgroi, F. De Bernardinis, S. F. Li, A. SangiovanniVincentelli, and J. Rabaey, "Wireless protocols design: Challenges and opportunities," presented at the 8th Int. Workshop Hardware/Software Co-Design Codes/CASHE'OO, San Diego, CA, May 2000.
11. C. G. Bell and A. Newell, Computer Structures: Readings and Examples. New York: McGraw-Hill, 1971.
12. A. Ferrari and A. Sangiovanni-Vincentelli, "System design: Traditional concepts and new paradigms," presented at the 1999 Int. Conf. Computer Design, Austin, TX, Oct. 1999.
13. H. Chang et al., Surviving the SOC Revolution: Platform-Based Design. Norwell, MA: Kluwer Academic, 1999.
14. R. Bryant, E. Clarice, and D. Dill, "GSRC formal verification effort," presented at the Annual GSRC Activities, San Jose, CA, Dec. 1999.
15. B. Dally and J. Rabaey, "The future of on-chip interconnection networks," presented at the GSRC quarterly meeting, Palo Alto, CA, Mar. 2000.
16. G. Bombarda, G. Gaviani, and P. Marceca, "Power-train system design: Functional and architectural specifications," presented at the Convergence 2000, Detroit, MI, Oct. 2000.
17. A. Sangiovanni-Vincentelli, "Automotive electronics: Trends and challenges," presented at the Convergence 2000, Detroit, MI, Oct. 2000.
18. J. Y. Brunei, A. Sangiovanni-Vincentelli, and R. Kress, "COSY: A methodology for system design based on reusable hardware & software IP's," in Technologies for the Information Society, J.-Y Roger, Ed. Singapore: IOS, June 1998, pp. 709-716.
19. J. Davis II, M. Goel, C. Hylands, B. Kienhuis, E. A. Lee, J. Liu, X. Liu, L. Muliadi, S. Neuendorffer, J. Reekie, N. Smyth, J. Tsay, and Y Xiong, "Overview of the Ptolemy Project," Dept. EECS, Univ. California, Berkeley, CA, ERL Tech. Rep. UCB/ERL no. M99/37, July 1999.
20. J. Rowson and A. Sangiovanni-Vincentelli, "Felix initiative pursues new co-design methodology," Electron. Eng. Times, p. 50, 51, 74, June 15, 1998.
21. VCC white papers. Cadence, San Jose, CA. [Online] . Available: http://www.cadence.com/whitepapers/vcc.html
22. E. A. de Kock, G. Essink, W. Smits, P. van der Wolf, J.-Y. Brunei, W. Kruijtzer, P. Lieverse, and K. Vissers, "YAPI: Application modeling for signal processing systems," presented at the Design Automation Conf. '2000, Los Angeles, CA, June 2000.
23. H. Renter, C. Passerone, W. Smits, Y Watanabe, and A. Sangiovanni-Vincentelli, "Designing digital video systems: Modeling and scheduling," presented at the CODES'99, Rome, Italy, May 1999.
24. J. Y Brunei, W. Kruijtzer, H. Renter, F. Petrot, L. Pasquier, E. de Kock, and W. Smits, "COSY communication IP's," presented at the Design Automation Conf. 2000, Los Angeles, CA, June 2000.
25. M. Baleani, A. Ferrari, A. Sangiovanni-Vincentelli, and C. Turchetti, "Hardware-software co-design of an engine management system," presented at the Design Automation and Test Europe Conf. 2000, France, Mar. 2000.
26. A. Ferrari, S. Garue, M. Peri, S. Pezzini, L. Valsecchi, F. Andretta, and W. Nesci, "Design and implementation of a dual-processor platform for power-train systems," presented at the Convergence 2000, Detroit, MI, Oct. 2000.
27. The Xtensa Processor Generator. Tensilica, Santa Clara, CA. [Online] . Available: http://www.tensilica.com/technology.html
28. The Silicon Backplane. Sonics, Inc., Mountain View, CA. [Online] . Available: http://www.sonicsinc.com
29. Commercial Video Processors. Massachusetts Institute of Technology, Cambridge, MA. [Online] . Available: http://wad.www.media.mit.edu/people/wad/vsp/node 1 .html
30. T. R. Halfhill, "Intel Network Processor Targets Routers,", vol. 13, Microprocessor Rep., Sept. 13, 1999.
31. "Hot Chips 99," Semiconductor Research Corp., San Jose, CA.
32. Univ. Illinois, The IMPACT Research Group., Urbana, IL. [Online] . Available: http://www.crhc.uiuc.edu/IMPACT
33. E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal, "Baring it all to software: Raw machines," IEEE Comput., pp. 86-93, Sept. 1997.
34. A. Sudarsanam, "Code Optimization Libraries for Retrgetable Compilation for Embedded Digital Signal Processors," Ph.D. dissertation, Princeton Univ., Princeton, NJ, Nov. 1998.
35. B. Kienhuis, E. Deprettere, K. Vissers, and P. van der Wolf, "An approach for quantitative analysis of application-specific dataflow architectures," presented at the 11th Int. Conf. Application-Specific Systems, Zurich, Switzerland, July 14-16, 1997.