Buffer implementation for Proteo networks-on-chip

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2003, Pages

  Saastamoinen, Ilkka ^a   Alho, Mikko ^a   Nurmi, Jari ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PACKET NETWORKS; SILICON;

NETWORK-ON-CHIP (NOC);

COMPUTER NETWORKS;

EID: 0038760864     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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