A network on chip architecture and design methodology

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2002-January, Issue , 2002, Pages 117-124

  Kumar, S ^a   Jantsch, A ^a   Soininen, J P ^b   Forsell, M ^b   Millberg, M ^a   Oberg J ^a   Tiensyrja K ^b   Hemani, A ^c  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

^c Spirea AB   (Sweden)

Author keywords

Communication switching; Computer architecture; Concrete; Design methodology; Field programmable gate arrays; Hardware; Network on a chip; Packet switching; Shape; Switches

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; COMPUTER HARDWARE; CONCRETE PRODUCTS; CONCRETES; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUIT TESTING; MEMORY ARCHITECTURE; MESH GENERATION; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; NETWORK LAYERS; NETWORK-ON-CHIP; PACKET SWITCHING; ROUTERS; SERVERS; SWITCHES; VLSI CIRCUITS;

COMMUNICATION SWITCHING; COMPUTATION RESOURCES; CONCRETE ARCHITECTURE; DESIGN METHODOLOGY; INTELLECTUAL PROPERTY BLOCKS; NETWORK ON A CHIP; NETWORK-ON-CHIP ARCHITECTURES; SHAPE;

INTEGRATED CIRCUIT DESIGN;

EID: 84948696213     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2002.1016885     Document Type: Conference Paper

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