Energy efficient signaling in deep submicron CMOS technology

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 319-324

  Dhaou, Imed Ben ^a   Sundararajan, Vijay ^b   Tenhunen, Hannu ^a   Parhi, Keshab K ^b  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY CONSERVATION; HEURISTIC ALGORITHMS;

CMOS PROCESSS; DEEP-SUBMICRON CMOS TECHNOLOGY; ENERGY EFFICIENT; LOW VOLTAGES; METAL LAYER; ON CHIP INTERCONNECT; ON-CHIP SIGNALING; SUPPLY VOLTAGES;

ENERGY EFFICIENCY;

EID: 84949962439     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915250     Document Type: Conference Paper

References (14)

1. W.J. Dally and J.W. Poulton, "Digital Systems Enginnering", Cambridge University Press 1998, ISBN 0521 59292 5
2. Tsu-Chang Lee, J. Cong, "The new line in IC design", Proc. IEEE Spectrum, pp: 52-58, Vol.: 343, March 1997
3. J. Pangjun and S.S. Sapatnekar "Clock distribution using multiple voltages" Proc. Int. Symp. On Low Power Elec. and Des., ISLPED'99, pp. 145-150
4. J.M. Rabaey, M. Pedram, "Low Power Design Methodologies", Kluwer Academic Publishers, 1996
5. Y.I. Ismail and E.G. Friedman, "Optimum Repeater Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect", Proc. ASIC Conf. 1998, pp. 369-373
6. A. Djordjevic, M. M. Baždar, T. K. Sarkar and R.F. Harrington, "LINPAR for Windows-Matrix Parameters for Multi conductor Transmission Lines-, Software and User's Manual, Version 2.0" Artech House, 1999, ISBN 1-58053-061-3
7. D. Zhou and X.Y. Liu, "Optimal Drivers for High-Speed Low Power ICs", Proc. Int. Journal of High Speed Electronics, 1995
8. C.K Cheng, J. Lillis, S. Lin and N. Chang, "Interconnect Analysis and Synthesis", John Wiley & Sons, 2000, ISBN Number: 0-471-29366-0
9. C. J. Alpert, A. Devgan and S. T. Quay, "Buffer Insertion for Noise and Delay Optimization", Proc. IEEE/ACM Des. Aut. Conf., DAC'98, pp. 362-367, June 1998
10. M. Kuhlmann, S. Sapatnekar and K.K. Parhi, "Efficient Crosstalk Estimation", Proc. of 1999 IEEE Int. Conf. on Computer Design, ICCD'99, pp. 266-272, Oct. 1999
11. R. Woonghwan, B. Seung-Ho Baik, K. Hyungsoo, K. Jonghoon Kim, M. Sung, and J. Kim, "Embedded microstrip interconnection lines for gigahertz digital circuits", Proc. IEEE Trans. On Packaging and Manufacturing Technology, Volume: 23 Issue: 3, pp. 495-503, Aug. 2000
12. T. Sakurai, "Closed-form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's", Proc. IEEE trans. On Electron Dev., pp. 118-124, Vol. 40, Jan. 1993
13. H. Zhou and D. F. Wong, "Optimal river routing with crosstalk constraints", Proc. ACM Trans. Des. Autom. Electron. Syst. 3, 3, pp. 496-514, Jul. 1998
14. I. Ben Dhaou and H. Tenhunen, "Energy Efficient High Speed On-Chip Signaling in Deep Submicron CMOS Technology", Proc. ACM/SIGDA, Sys. Level Int. Pred., SLIP2000, pp. 69-76, April 2000