An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 250-255

  Han, Sang Il ^a,b   Baghdadi, Amer ^c   Bonaciu, Marius ^b   Chae, Soo Ik ^a   Jerraya, Ahmed A ^b  

^a Seoul National University   (South Korea)

^b TIMA LABORATORY   (France)

^c ECOLE DES MINES DE NANTES   (France)

Author keywords

Data transfer architecture; Memory Server; Message passing; Multiprocessor SoC; Network Interface; Network on chip

Indexed keywords

BANDWIDTH; COMPUTATIONAL COMPLEXITY; DATA COMMUNICATION SYSTEMS; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; SCHEDULING; SERVERS; THROUGHPUT;

DATA TRANSFER ARCHITECTURE; MEMORY SERVER; MESSAGE PASSING; MULTIPROCESSOR SOC; NETWORK INTERFACE; NETWORK ON CHIP;

DATA TRANSFER;

EID: 4444343175     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996636     Document Type: Conference Paper

References (19)

1. K. Keutzer et al. "System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. On CAD of Integrated Circuits and Systems.
2. Culler D. E. et al, "Parallel Computer Architecture, A Hardware/software approach," Morgan Kaufmann Inc, San Francisco California, 1999, ISBN 1-55860-343-3.
3. A. Baghdadi, D. Lyonnard, N.-E. Zergainoh, and A.A. Jerraya, "An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC," in Proceedings of DATE'01.
4. Jerraya et al., "Component-Based Design Approach for Multicore SoCs," in Proceedings of DAC'02.
5. ARM PrimeCell™ DMA Controller, http://www.arm.com/armtech/PrimeCell?OpenDocument
6. Dave Comisky et al, "A Scalable High-Performance DMA Architecture for DSP Applications," in Proceedings of ICCD 2000.
7. MemMax™ Memory Scheduler, http://www.sonicsinc.com/sonics/products/memmax
8. A. Radulescu et al, "An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming," in Proceedings of DATE'04.
9. P. Bhojwani et al. "Interfacing cores with on-chip packet-switched networks," In IEEE Proc. On VLSI Design, 2003
10. E. Rijpkema, et al., "Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip," in Proceedings of DATE'03.
11. William J. Dally and Brian Towles,"Route Packets, Not Wires: On-Chip Interconnection Networks," in Proceedings of DAC'02.
12. Philips Nexperia™ DVP, http://www.semiconductors.philips.com/platforms/nexperia
13. TI OMAP™ Platform, http://www.ti.com/sc/docs/apps/omap/overview.htm
14. MPEG-4 Standard, http://www.chiariglione.org/mpeg/standards/mpeg-4/mpeg-4.htm
15. Motorola DSP56311, http://www.motorola.com/brdata/PDFDB/docs/DSP56311.pdf
16. ARM ARM946E-S, http://www.arm.com/products/CPUs/ARM946ES.html
17. T. McMahon, A. Skjellum, "eMPI/eMPICH: Embedding MPI," In Proceedings of the Second MPI Developer's Conference, University of Notre Dame, South Bend, IN, 1996, pp. 57-65. 22
18. J. Kohout and A. George, "A High-Performance Communication Service for Parallel Computing on Distributed DSP Systems," Parallel Computing, Vol. 29, No. 7, July 2003, pp. 851-878.
19. Junyu Peng and Daniel Gajski. "Optimal Message-Passing for Data Coherency in Distributed Architecture," in Proceedings of ISSS'02.