Micro-network for SoC: Implementation of a 32-port SPIN network

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 1128-1129

  Andriahantenaina, Adrijean ^a   Greiner, Alain ^a  

^a SORBONNE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; INTEGRATED NETWORKS; METAL LAYER; METAL PROCESS; ROUTING WIRES; SPIN NETWORKS; ST MICROELECTRONICS; SWITCHING COMPONENTS;

CMOS INTEGRATED CIRCUITS; MICROELECTRONICS;

EXHIBITIONS;

EID: 84893818178     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253766     Document Type: Conference Paper

References (7)

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2. A. Andriahantenaina. SPIN: Technical report. Pierre and Marie CURIE University, Paris, France, 2002
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5. P. Guerrier and A. Greiner. A genericar chitecture for onchip packet-switched interconnections. Proceedings of the Design Automation and Test in Europe Conference 2000 (DATE?2000), Paris, France, pages 250-256, Mars 2000
6. J. Hennessy and D. Patterson. Computer Architecture, A Quantitative Approach - 2nd Edition. Morgan Kaufmann Publishers, San Francisco, CA, USA, 1996
7. C. Leiserson. Fat-trees: Universal networks for hardwareefficient supercomputing. IEEE Transactions on Computers, vol. C-34, no. 10, pages 892-901, October 1985