A look into the future of nanoelectronics

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 6-10

  Declerck, Gilbert ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; ELECTRIC NETWORK ANALYSIS; MATERIALS SCIENCE; NANOSTRUCTURED MATERIALS;

MATERIALS SCIENCE BASED ENGINEERING; NANOELECTRONICS; NOMADIC CONNECTIVITY;

VLSI CIRCUITS;

EID: 33745116218     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469191     Document Type: Conference Paper

References (18)

1. G. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, pp. 114-117, 1965;
2. see also G. Moore, "Progress in digital integrated electronics," IEEE IEDM Tech. Digest, pp. 11-13, 1975
3. R. Dennard et al. "Design of ion-implanted MOSFETs with very small dimensions," IEEE J. Solid-St. Circuits, vol. 9, 256, 1974.
4. D.L. Critchlow, "MOSFET scaling - The driver of VLSI technology", Proc. IEEE, vol. 87, pp. 659-667, 1999.
5. P. Gelsinger, "Microprocessors for the new millennium: challenges, opportunities and new frontiers", ISSCC Digest of Techn. Papers, pp. 22-25, 2001.
6. T. Sakurai, "Perspectives on power-aware electronics", ISSCC Digest of Techn. Papers, pp. 26-29, 2003.
7. J. Rabaey, "Design at the end of the silicon roadmap", Keynote Presentation, ASPDAC, Shanghai, January 2005.
8. E. Aarts, R. Harwig and M. Schuurmans, "Ambient Intelligence" in The Invisible Future, P. Denning, Ed., McGraw Hill, New York, pp. 235-250, 2001.
9. T. Claasen, "High speed: not the only way to exploit the intrinsic computational power of silicon", ISSCC Digest of Techn. Papers, pp. 22-25, 1999.
10. P.M. Zeitzoff, J.A. Hutchby and H.R. Huff, "MOSFET and front-end process integration: scaling trends, challenges, and potential solutions through the end of the roadmap," Int. J. of High-Speed Electronics and Systems, vol. 12, pp. 267-293, 2002.
11. P. Leunissen, M. Ercken and G. Patsis, "Determining the influence of statistical fluctuations on resist line edge roughness", presented at MNE 2004 (Rotterdam, The Netherlands), to be published in Microelectronic Engineering, 2005.
12. Babak Amir Parviz, Declan Ryan and George M. Whitesides, "Using self-assembly for the fabrication of nano-scale electronic and photonic devices", IEEE Trans. On Adv. Packaging, vol. 26, pp. 233-241, 2003.
13. M. Pelgrom et al., "Matching properties of MOS transistors", IEEE J. Solid-St. Circuits, vol. 24, pp. 1433-1440, 1989.
14. K. Itoh et al., "Review and future prospects of low-voltage embedded RAMs", Digest of CICC, Oct 2004.
15. M. Yamaoka et al., "Low power SRAM menu for SoC application using ying-yang feedback memory cell", Digest Symp. VLSI Circuits, pp. 288-291, June 2004.
16. L. Chang et al., "Moore's law lives on", IEEE Circuits and Dev. Mag., vol. 19, pp. 35-42, 2003.
17. 2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75 NA 193nm lithography", IEEE IEDM Tech. Digest, pp. 269-272, 2004;
18. (b) L. Witters et al., this symposium.