A methodology for designing efficient on-chip interconnects on well-behaved communication patterns

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 12, Issue , 2003, Pages 377-388

  Ho, Wai Hong ^a   Pinkston, T M ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Communication switching; Computer networks; Design methodology; Design optimization; Network topology; Network on a chip; Resource management; Sufficient conditions; Switches; Wires

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTER RESOURCE MANAGEMENT; DESIGN; DISTRIBUTED COMPUTER SYSTEMS; MESH NETWORKING; NETWORK ARCHITECTURE; SUPERCOMPUTERS; SWITCHES; TOPOLOGY; WIRE;

COMMUNICATION SWITCHING; DESIGN METHODOLOGY; DESIGN OPTIMIZATION; NETWORK ON A CHIP; NETWORK TOPOLOGY; RESOURCE MANAGEMENT; SUFFICIENT CONDITIONS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84955516546     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2003.1183554     Document Type: Conference Paper

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