Methodologies and tools for pipelined on-chip interconnect

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 152-157

  Scheffer, Lou ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; LOGIC DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

COMBINATORIAL OPTIMIZATION; ON-CHIP INTERCONNECT;

INTERCONNECTION NETWORKS;

EID: 0036398242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. D. Abts and M. Roberts. Verifying large-scale multi-processors using an abstract verification environment. In Proc. 36th Design Automation Conference, pages 163-168, 1999.
2. L. P. Carloni, K. L. McMillan, A. Saldanha, and A. L. Sangiovanni-Vincentelli. A methodology for correct-by-construction latency-insensitive design. In Proc. ICCAD, San Jose, CA, November, 1999.
3. L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli. Latency insensitive protocols. In Proc. Int. Conf. Computer-Aided Verification, Trento, Italy, 1999.
4. L.P. Carloni, K.L. McMillan, and A.L. Sangiovanni-Vincentelli. Theory of latency-insensitive design. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 20(9), September 2001.
5. D. G. Chinnery and K. Keutzer. Closing the gap between ASIC and custom: An ASIC perspective. In Proceeding of the Design Automation Conference, pages 637-642, June 2000.
6. A. Clouard, G. Mastrorocco, F. Carbognani, and F. Ghenassia. Towards bridging the precision gap between SoC transactional and cycle-accurate levels. In Proc. Design, Automation and Test in Europe Conference, March 2002.
7. L. Drucker and K. Karnane. How transaction-based verification works. EEdesign March 22, 2002. http://www.eedesign.com/features/exclusive/OEG20020322S0101.
8. M. Kudlugi, S. Hassoun, C. Selvidge, and D. Pryor. A transaction-based unified simulation/emulation architecture for functional verification. In Proc. Design Automation Conference, pages 623-628, 2001.
9. J. Levitt and K. Olukotun. Verifying correct pipeline implementation for microprocessors. In Proc of IEEE/ACM International Conference on Computer-Aided Design, pages 162-169, 1997.
10. R. Lu, G. Zhong, C.-K. Koh, and K.-Y. Chao. Flip-flop and repeater insertion for early interconnect planning. In Proc. Design, Automation and Test in Europe Conference, pages 690-695, March 2002.
11. ™ microprocessor. In International Symposium on Physical Design, pages 99-104, 2000.
12. R. Ranjan, V. Singhal, F. Somenzi, and R. Brayton. Using combinational verification for sequential circuits. In Proc. Design, Automation and Test in Europe Conference and Exhibition, pages 138-144, 1999.
13. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 1999.
14. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2001.
15. Silicon Integration Initiative (Si2). http://www.openeda.org,2002.
16. S. W. Smith. Verification transactions call for higher abstraction. EE Times, June 9 2000.
17. H. Tomiyama, T. Yoshino, and N. Dutt. Verification of in-order execution in pipelined processors. In Proc. of the IEEE High-Level Design Validation and Test Workshop, pages 40-44, 2000.
18. M. Velev and R. Bryant. Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors. In Proc. of the 36th Design Automation Conference, pages 397-401, 1999.
19. White Paper, Cadence Design Systems. Transaction Based Verification. http://www.cadence.com/whitepapers/transac.html.