Cost considerations in network on chip

Integration, the VLSI Journal

Volumn 38, Issue 1, 2004, Pages 19-42

  Bolotin, Evgeny ^a   Cidon, Israel ^a   Ginosar, Ran ^a   Kolodny, Avinoam ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Cost minimization; Network on chip; Scalable interconnect; Wormhole buffering

Indexed keywords

CHANNEL CAPACITY; COSTS; INTERCONNECTION NETWORKS; PACKET NETWORKS; QUALITY OF SERVICE; QUENCHING; SYNCHRONIZATION; VLSI CIRCUITS;

COST MINIMIZATION; NETWORK ON CHIP; SCALABLE INTERCONNECTS; WORMHOLE BUFFERING;

MICROPROCESSOR CHIPS;

EID: 9544239365     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2004.03.006     Document Type: Article

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