A global wiring paradigm for deep submicron design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 2, 2000, Pages 242-252

  Sylvester, Dennis ^a   Keutze, Kurt ^b  

^a SYNOPSYS INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Integrated circuit interconnections; Integrated circuit modeling; Routing; Ultra large scale integration

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC RESISTANCE; INTERCONNECTION NETWORKS; SEMICONDUCTOR DEVICE MANUFACTURE; SPURIOUS SIGNAL NOISE; ULSI CIRCUITS;

DEEP SUBMICROMETERS; GLOBAL WIRING; RESISTANCE CAPACITANCE DELAY; ROUTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033903824     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.828553     Document Type: Article

References (20)

1. D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," in Proc. ICCAD, 1998, pp. 203-211.
2. "National Technology Roadmap for Semiconductors," Semiconductor Industry Association, San Jose, CA, 1997.
3. M. Bohr et al, "A high performance 0.25 ftm logic technology optimized for 1.8 V operation," in Proc. IEDM. 1996, pp. 847-850.
4. R. Otten, "Global wires: Harmful?," in Proc. Int. Symp. Physical Design, 1998, pp. 104-109.
5. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
6. G. A. Sai-Halasz, "Performance trends in high-end processors," Proc. IEEE, pp. 20-36, Jan. 1995.
7. N. Vasseghi, K. Yeager, E. Sarto, and M. Seddighnezhad, "200-MHz superscalar RISC microprocessor," IEEEJ. Solid-State Circuits, vol. 31, pp. 1675-1685, Nov. 1996.
8. P. Zarkesh-Ha and J. D. Meindl, "Stochastic net length distributions for global interconnects in a heterogeneous system-on-a-chip," in Proc. VLSI Symp. Tech., 1998, pp. 44-45.
9. D. Sylvester, C. Hu, O. S. Nakagawa, and S. Y. Oh, "Interconnect scaling: Signal integrity and performance in future high-speed CMOS designs," in Proc. VLSI Symp. Technol., 1998, pp. 42-43.
10. W. E. Donath, "Placement and average interconnection lengths of computer logic," IEEE Trans. Circuits and Systems, vol. 26, pp. 272-277', Apr. 1979.
11. S.-Y. Kim, N. Gopal, and L. Pillegi, "Time-domain macromodels for VLSI interconnect analysis," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1257-1270, Oct. 1994.
12. Y I. Ismail, E. G. Friedman, and J. L. Neves, "Figures of merit to characterize the importance of on-chip inductance," in Proc. DAC, 1998, pp. 560-565.
13. Y Massoud, S. Majors, T. Bustami, and J. White, "Layout techniques for minimizing on-chip interconnect self-inductance," in Proc. DAC, 1998, pp. 566-571.
14. D. W. Bailey and B. J. Benschneider, "Clocking design and analysis for a 600-MHz Alpha microprocessor," IEEE J. Solid-State Circuits, vol. 33, pp. 1627-1633, Nov. 1998.
15. Berkeley Advanced Chip Performance Calculator. Univ. California, Berkeley, CA. [Online]. Available: http://www-device.eecs.berkeley.edu/~dennis/BACPAC.
16. T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118-124, Jan. 1993.
17. Q. Zhu and S. Tarn, "Package clock distribution design optimization for high-speed and low-power VLSI's," IEEE Trans. Comp., Packag., Manufact. Technol., vol. 20, pp. 56-63, Feb. 1997.
18. R. R. Tummala and E. Rymaszewski, Microelectronics Packaging Handbook. New York: Van Nostrand Reinhold, 1989.
19. O. S. Nakagawa, D. Sylvester, J. G. McBride, and S.-Y. Oh, "Closed-form modeling of on-chip crosstalk noise in deep submicron ULSI interconnect," Hewlett-Packard J. Res. Develop., pp. 3915, Aug. 1998.
20. W. S. Song and L. A. Classer, "Power distribution techniques for VLSI circuits," IEEE J. Solid-State Circuits, vol. 21, pp. 150-156, Feb. 1986.