Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 350-355

  Rijpkema, E ^a   Goossens, K G W ^a   Radulescu A ^a   Dielissen, J ^a   Van Meerbergen, J ^a   Wielage, P ^a   Waterlander, E ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BEST-EFFORT SERVICES; EFFICIENT IMPLEMENTATION; GUARANTEED SERVICE; GUARANTEED THROUGHPUTS; HARDWARE COMPLEXITY; RESOURCE UTILIZATIONS; ROUTER ARCHITECTURE; SHARING RESOURCES;

COMMERCE; COMMUNICATION; DESIGN; EXHIBITIONS;

ROUTERS;

EID: 84893753441     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253633     Document Type: Conference Paper

References (16)

1. M. Ali and M. Youssefi. The performance analysis of an input access scheme in a high-speed packet switch. In INFOCOM, 1991.
2. J. Bainbridge and S. Furber. CHAIN: A delay-insensitive chip area interconnect. IEEE Micro, (5), 2002.
3. L. Benini and G. De Micheli. Powering networks on chips. In ISSS, 2001.
4. L. Benini and G. De Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70-80, 2002.
5. W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In DAC, 2001.
6. A. deHon. Robust, high-speed network design for large-scale multiprocessing. TR 1445, MIT, AI Lab., 1993.
7. K. Goossens et al. Networks on silicon: Combining best-effort and guaranteed services. In DATE, 2002.
8. P. Guerrier and A. Greiner. A generic architecture for on-chip packet-switched interconnections. In DATE, 2000.
9. M. J. Karol et al. Input versus output queueing on a spacedivision packet switch. IEEE Trans. on Communications, COM-35(12):1347-1356, 1987.
10. K. Keutzer et al. System-level design: Orthogonalization of concerns and platform-based design. IEEE Trans. on CAD of Integrated Circuits and Systems, 19(12):1523-1543, 2000.
11. N. McKeown. Scheduling Algorithms for Input-Queued Cell Switches. PhD thesis, Univ. of California, Berkeley, 1995.
12. J. Rexford. Tailoring Router Architectures to Performance Requirements in Cut-Through Networks. PhD thesis, Univ. Michigan, 1999.
13. M. T. Rose. The Open Book: A Practical Perspective on OSI. 1990.
14. M. Sgori et al. Addressing the system-on-A-chip interconnect woes through communication-based design. In DAC, 2001.
15. A. S. Tanenbaum. Computer Networks. 1996.
16. H. Zhang. Service disciplines for guaranteed performance service in packet-switching networks. Proc. of the IEEE, 83(10):1374-96, 1995.