Making typical silicon matter with razor

Computer

Volumn 37, Issue 3, 2004, Pages 57-65

  Austin, Todd ^a   Blaauw, David ^a   Mudge, Trevor ^a   Flautner, Krisztián ^b  

^a University of Michigan   (United States)

^b ARM LTD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL LOGIC; SIMULATION PROGRAM WITH INTEGRATED EMPHASIS; TIMING-ERROR DETECTION; VOLTAGE SCALING;

CAPACITANCE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC FAULT LOCATION; ELECTRIC POTENTIAL; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MULTIPLEXING EQUIPMENT; PIPELINE PROCESSING SYSTEMS; SHIFT REGISTERS;

SEMICONDUCTING SILICON;

EID: 1842582489     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2004.1274005     Document Type: Article

References (11)

1. D. Ernst et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," Proc. 36th Ann. Int'l Symp. Microarchitecture (MICRO-36), IEEE CS Press, 2003, pp. 7-18.
2. T. Mudge, "Power: A First-Class Architectural Design Constraint," Computer, Apr. 2001, pp. 52-58.
3. R.F. Sproull, I.E. Sutherland, and C.E. Molnar, "The Counterflow Pipeline Processor Architecture," IEEE Design and Test of Computers, Fall 1994, pp. 48-59.
4. K. Flautner and T. Mudge, "Vertigo: Automatic Performance-Setting for Linux," Proc. 5th Conf. Operating Systems Design and Implementation (OSDI), ACM Press, 2002, pp. 105-116.
5. K. Flautner et al., to appear in "IEM 926: An Energy-Efficient SoC with Dynamic Voltage Scaling," Proc. Design Automation and Test in Europe (DATE-2004), IEEE CS Press, 2004.
6. N. Kim et al., "Drowsy Instruction Caches: Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Subbank Prediction," Proc. 35th Ann. IEEE/ACM Symp. Microarchitecture (MICRO-35), IEEE CS Press, 2002, pp. 219-230.
7. K. Flautner et al., "Drowsy Caches: Simple Techniques for Reducing Leakage Power," Proc. 29th Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 2002, pp. 148-157.
8. J. Ziegler et al., "IBM Experiments in Soft Fails in Computer Electronics," IBM J. Research and Development, Jan. 1996, pp. 3-18.
9. P. Rubinfeld, "Managing Problems at High Speed," Computer, Jan. 1998, pp. 47-48.
10. T. May and M. Woods, "Alpha-Particle-Induced Soft Errors in Dynamic Memories," IEEE Trans. Electron Devices, vol. 26, no. 2, 1979, pp. 2-9.
11. J. Ziegler, "Terrestrial Cosmic Rays," IBM J. Research and Development, Jan. 1996, pp. 19-39.