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Volumn , Issue , 2004, Pages 448-451

SILENT: Serialized low energy transmission coding for on-chip interconnection networks

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); CROSSTALK; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; MULTIPLEXING; PACKET SWITCHING; SYNCHRONIZATION; THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 16244392403     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (74)

References (8)
  • 1
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    • An 800MHz star-connected on-chip network for application to systems on a chip
    • S.J. Lee, et al., "An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip," ISSCC Dig. of Tech. Papers, pp. 468-469, 2003
    • (2003) ISSCC Dig. of Tech. Papers , pp. 468-469
    • Lee, S.J.1
  • 2
    • 0032202850 scopus 로고    scopus 로고
    • A 2.6-GByte/s multipurpose chip-to- Chip interface
    • Nov.
    • B. Lau, et al., "A 2.6-GByte/s Multipurpose Chip-to- Chip Interface," Journal of Solid-State Circuits, vol.33, no. 11, Nov. 1998
    • (1998) Journal of Solid-State Circuits , vol.33 , Issue.11
    • Lau, B.1
  • 3
    • 0038645209 scopus 로고    scopus 로고
    • An on-chip high speed serial communication method based on independent ring oscillators
    • S. Kimura, et al., "An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators," ISSCC Dig. of Tech. Papers, pp. 390-391, 2003
    • (2003) ISSCC Dig. of Tech. Papers , pp. 390-391
    • Kimura, S.1
  • 4
    • 0000440896 scopus 로고
    • Architectural power analysis: The dual bit type method
    • June
    • P. E. Landman, and J. M. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method," Transactions on VLSI Systems, vol.3, no.2, June 1995
    • (1995) Transactions on VLSI Systems , vol.3 , Issue.2
    • Landman, P.E.1    Rabaey, J.M.2
  • 5
    • 0031342532 scopus 로고    scopus 로고
    • Low-power encoding for global communication in CMOS VLSI
    • June
    • M. R. Stan, et al., "Low-Power Encoding for Global Communication in CMOS VLSI," Transactions on VLSI Systems, vol.5, no.4, June 1997
    • (1997) Transactions on VLSI Systems , vol.5 , Issue.4
    • Stan, M.R.1
  • 7
    • 0037631130 scopus 로고    scopus 로고
    • A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications
    • R. Woo, et al., "A 210mW Graphics LSI Implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications," ISSCC Dig. of Tech. Papers, pp. 44-45, 2003
    • (2003) ISSCC Dig. of Tech. Papers , pp. 44-45
    • Woo, R.1
  • 8
    • 2442698800 scopus 로고    scopus 로고
    • A 51mW 1.6GHz network for low-power heterogeneous SoC platfrom
    • K. Lee, et al., "A 51mW 1.6GHz Network for Low-Power Heterogeneous SoC Platfrom," ISSCC Dig. of Tech. Papers, pp. 152-153, 2004
    • (2004) ISSCC Dig. of Tech. Papers , pp. 152-153
    • Lee, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.