메뉴 건너뛰기




Volumn , Issue , 2003, Pages 146-150

Efficient synthesis of networks on chip

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; MICROPROCESSOR CHIPS; OPTIMIZATION; QUADRATIC PROGRAMMING;

EID: 0344119476     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (123)

References (10)
  • 2
    • 0345461374 scopus 로고    scopus 로고
    • Networks on-chips: A new soc paradigm
    • January
    • L. Benini and G. De-Micheli. Networks on-chips: A new soc paradigm. IEEE Computer, January 2002.
    • (2002) IEEE Computer
    • Benini, L.1    De-Micheli, G.2
  • 6
    • 33646922057 scopus 로고    scopus 로고
    • The future of wires
    • Apr.
    • R. Ho, K. Mai, and M. Horowitz. The Future of Wires. Proc. of the IEEE, 89(4):490-504, Apr. 2001.
    • (2001) Proc. of the IEEE , vol.89 , Issue.4 , pp. 490-504
    • Ho, R.1    Mai, K.2    Horowitz, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.