Energy-aware mapping for tile-based NoC architectures under performance constraints

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 233-239

  Hu, Jingcao ^a   Marculescu, R ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BRANCH AND BOUND METHOD; COMPLEX NETWORKS; COMPUTER AIDED DESIGN; ENERGY CONSERVATION; MAPPING; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; POWER MANAGEMENT; POWER MANAGEMENT (TELECOMMUNICATION); PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; VLSI CIRCUITS;

AD HOC IMPLEMENTATION; BANDWIDTH RESERVATION; BRANCH-AND-BOUND ALGORITHMS; COMMUNICATION ENERGY; ENERGY AWARE; NOC ARCHITECTURES; PERFORMANCE CONSTRAINTS; REGULAR NETWORKS;

NETWORK-ON-CHIP;

EID: 84954421164     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195022     Document Type: Conference Paper

References (10)

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