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Volumn , Issue , 2002, Pages 8-12

Coding scheme for low energy consumption fault-tolerant bus

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; BUSES; CMOS INTEGRATED CIRCUITS; ENERGY UTILIZATION; ERROR CORRECTION; FAULT TOLERANCE; OPTIMAL SYSTEMS;

EID: 84962752543     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2002.1030176     Document Type: Conference Paper
Times cited : (30)

References (15)
  • 3
    • 0035967021 scopus 로고    scopus 로고
    • Fast, Minimal Decoding Complexity, Systematic (13,8) Singlw-Error-Correcting Code for On-Chip DRAM Application
    • 29th March
    • A. Kazeminejad. Fast, Minimal Decoding Complexity, Systematic (13,8) Singlw-Error-Correcting Code for On-Chip DRAM Application. Electronic Letters, 29th March 2001.
    • (2001) Electronic Letters
    • Kazeminejad, A.1
  • 5
    • 0032317504 scopus 로고    scopus 로고
    • On-Line Detection of Logic Errors due to Crosstalk, Delay, and Transient Faults
    • C. Metra, M. Favalli, and B. Riccò. On-Line Detection of Logic Errors due to Crosstalk, Delay, and Transient Faults. In Proc. of IEEE Int. Test Conf., pages 524-533, 1998.
    • (1998) Proc. of IEEE Int. Test Conf. , pp. 524-533
    • Metra, C.1    Favalli, M.2    Riccò, B.3
  • 6
    • 0034204994 scopus 로고    scopus 로고
    • Self-checking detection and diagnosis scheme for transient, delay and crosstalk faults affecting bus lines
    • June
    • C. Metra, M. Favalli, and B. Riccò. Self-checking detection and diagnosis scheme for transient, delay and crosstalk faults affecting bus lines. IEEE Trans. Comput., pages 560-574, June 2000.
    • (2000) IEEE Trans. Comput. , pp. 560-574
    • Metra, C.1    Favalli, M.2    Riccò, B.3
  • 7
    • 0032684765 scopus 로고    scopus 로고
    • Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
    • M. Nicolaidis. Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies. In Proc. of IEEE VLSI Test Symp., 1999.
    • (1999) Proc. of IEEE VLSI Test Symp.
    • Nicolaidis, M.1
  • 12
    • 34548834356 scopus 로고    scopus 로고
    • Transition Pattern Coding: An Approach to Reduce Energy in Interconnect
    • Stockholm, Sweden
    • P. P. Sotiriadis, A. Wang, and A. Chandrakasan. Transition Pattern Coding: An Approach to Reduce Energy in Interconnect. In ESSCIRC 2000, Stockholm, Sweden, 2000.
    • (2000) ESSCIRC 2000
    • Sotiriadis, P.P.1    Wang, A.2    Chandrakasan, A.3
  • 13
    • 0031342532 scopus 로고    scopus 로고
    • Low-Power Encodings for Global Communication CMOS VLSI
    • December
    • M. R. Stan and W. P. Burleson. Low-Power Encodings for Global Communication CMOS VLSI. IEEE Trans. on VLSI Systems, December 1997.
    • (1997) IEEE Trans. on VLSI Systems
    • Stan, M.R.1    Burleson, W.P.2
  • 14
    • 33747740078 scopus 로고    scopus 로고
    • Theory and Design of Adjacent Asymmetric Error Masking Codes
    • May
    • L. G. Tallini and B. Bose. Theory and Design of Adjacent Asymmetric Error Masking Codes. IEEE Trans. on Computers, May 1998.
    • (1998) IEEE Trans. on Computers
    • Tallini, L.G.1    Bose, B.2
  • 15
    • 10944268341 scopus 로고    scopus 로고
    • Reduction of Interconnect Delay by Exploiting Cross-talk
    • S. van Dijk and D. Hely. Reduction of Interconnect Delay by Exploiting Cross-talk. In Proc. of ESSCIRC2001, pages 316-319, 2001.
    • (2001) Proc. of ESSCIRC2001 , pp. 316-319
    • Van Dijk, S.1    Hely, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.