Interfacing cores with on-chip packet-switched networks

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 382-387

  Bhojwani, P ^a   Mahapatra, R ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Assembly; Communication switching; Delay; Logic; Network on a chip; Parallel processing; Routing; Scalability; System on a chip; Tiles

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ASSEMBLY; DESIGN; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; PACKET NETWORKS; PROGRAMMABLE LOGIC CONTROLLERS; SCALABILITY; SWITCHING CIRCUITS; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS; TILE;

COMMUNICATION SWITCHING; DELAY; LOGIC; NETWORK ON A CHIP; PARALLEL PROCESSING; ROUTING; SYSTEM ON A CHIP;

NETWORK-ON-CHIP;

EID: 84941344008     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183166     Document Type: Conference Paper

References (9)

1. G. De Micheli and L. Benini, "Networks on Chip: A New SOC Paradigm", IEEE Computer, Vol. 35 Issue: 1, Jan 2002, pp. 70-78
2. L. Benini and G. De Micheli, "Powering Networks on Chips", System Synthesis, 2001. Proceedings, The 14th International Symposium on, 2001, pp. 33-38.
3. P. Guerrier and A. Greiner, "A generic architecture for on-chip packet-switched interconnections", Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000, pp. 250-256.
4. W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks", Design Automation Conference, 2001. Proceedings, 2001, pp. 684-689.
5. Sgroi, M., et. al., "Addressing the system-on-a-chip interconnect woes through communication-based design", Design Automation Conference, 2001. Proceedings, 2001, pp. 667-672.
6. N. Swaminathan, "Communication Synthesis for On-Chip Networks", Masters Thesis, Texas A&M University, 2002.
7. Tensilica Xtensa Core, www.tensilica.com
8. VSI Alliance, Virtual Component Interface Standard Version 2 (OCB 2 2.0), April 2001. www.vsi.org [Document is only available to members]
9. Kumar S., et. al., "A Network on Chip Architecture and Design Methodology", Proceedings of IEEE Computer Society Annual Symposium on VLSI, April 2002.