StepNP: A system-level exploration platform for network processors

IEEE Design and Test of Computers

Volumn 19, Issue 6, 2002, Pages 17-26

  Paulin, Pierre G ^a   Pilkington, Chuck ^a   Bensoudane, Essaid ^a  

^a STMICROELECTRONICS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; INTERFACES (COMPUTER); MULTIPROCESSING SYSTEMS; PACKET NETWORKS; PROGRAM DEBUGGING; REDUCED INSTRUCTION SET COMPUTING;

NETWORK PROCESSORS;

NETWORK PROTOCOLS;

EID: 0036857007     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2002.1047740     Document Type: Article

References (8)

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3. L. Benini and G. De Micheli, "Networks on Chip: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-72.
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6. A. Clouard et al., "Towards Bridging the Gap between SoC Transactional and Cycle-Accurate Levels," Proc. Design, Automation, and Test in Europe Designer Forum, DATE Conf. Secretariat, Edinburgh, UK, 2002, pp. 22-29.
7. E. Kohler et al., "The Click Modular Router," ACM Trans. Computer Systems. vol. 18, no. 3, Aug. 2000. pp. 263-297.
8. J.L. Hennessy et al., Computer Architecture: A Quantitative Approach, Morgan Kaufmann. San Mateo, Calif., 1990.