Test infrastructure design for the NexperiaTM home platform PNX8550 system chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 3, Issue , 2004, Pages 108-113

  Goel, Sandeep Kumar ^a   Chiu, Kuoshu ^b   Marinissen, Erik Jan ^a   Nguyen, Toan ^b   Oostdijk, Steven ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED DESIGN; MANUFACTURING TESTS; MODULAR TESTING; SOC TESTS; TEST ACCESS MECHANISM; TEST APPLICATION TIME; TEST ARCHITECTURE; TEST INFRASTRUCTURES;

COMMERCE; DESIGN; EXHIBITIONS; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS;

TESTING;

EID: 84893756521     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269215     Document Type: Conference Paper

References (13)

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3. Erik Jan Marinissen and Harald Vranken. On the Role of DfT in IC-ATE Matching. In Digest of Papers of IEEE International Workshop on Test Resource Partitioning (TRP), Baltimore, MD, November 2001.
4. Santanu Dutta, Rune Jensen, and Alf Rieckmann. VIPER: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems. IEEE Design & Test of Computers, 18(5):21-31, Sep-Oct 2001.
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12. Sandeep Kumar Goel and Erik Jan Marinissen. Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. In Proceedings Design, Automation, and Test in Europe (DATE), pages 738-743, Munich, Germany, March 2003.
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