Theory of latency-insensitive design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 9, 2001, Pages 1059-1076

  Carloni, Luca P ^a,b   McMillan, Kenneth L ^b   Sangiovanni Vincentelli, Alberto L ^a,c  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Deep submicrometer design; Formal methods; Latency insensitive protocols; System design

Indexed keywords

DEEP SUBMICROMETER DESIGN;

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTATION THEORY; LARGE SCALE SYSTEMS; NETWORK PROTOCOLS;

COMPUTER AIDED DESIGN;

EID: 0035441059     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.945302     Document Type: Article

References (44)

1. Challenges and opportunities for design innovations in nanometer technologies
2. Using partitioning to help convergence in the standard-cell design automation method
3. Interconnect scaling - The real limiter to high performance ULSI
4. Interconnect scaling implications for CAD
5. Silicon trends and limits for advanced microprocessors
6. Deep-submicron microprocessor design issues
7. The future of wires
8. Will physical scalability sabotage performance gains?
9. Clock rate versus ipc: The end of the road for conentional microarchitectures
10. The architecture of pipelined computers
11. Pentium 4 (partially) previewed
12. Latency insensitive protocols
13. A methodology for 'correct-by-construction' latency insensitive design
14. Asynchronous circuit design: Motivation, background, and methods
15. Asynchronous design methodologies: An overview
16. Macromodular computer systems
17. The promise of macromodular systems
18. Synthesis of delay-insensitive modules
19. Q-modules: Internally clocked delay-insensitive modules
20. A formal model for defining and classifying delay-insensitive circuits
21. On the delay-sensitivity of gate networks
22. The limitations to delay-insensitivity in asynchronous circuits
23. A formal approach to designing delay-insensitive circuits
24. An overview of DI algebra
25. Automatic gate-level synthesis of speed-independent circuits
26. Trace theory for automatic hierarchical verification of speed-independent circuits
27. Basic gate implementation of speed-independent circuits
28. Trace theory and VLSI design
29. Relative scheduling under timing constraints
30. Interface optimization for concurrent systems under timing constraints
31. A framework for comparing models of computation
32. Hybrid dynamical systems theory and the signal language
33. Compositional model checking
34. A compositional rule for hardware design refinement
35. Verification of an implementation of Tomasulo's algorithm by compositional model checking
36. You assume, we guarantee: Methodology and case studies
37. A 600 MHz superscalar RISC microprocessor with out-of-order execution
38. An efficient algorithm for exploiting multiple arithmetic units
39. The alpha 21 264 microprocessor
40. BONeS DESIGNER: A graphical environment for discrete-event modeling and simulation