Coding for system-on-chip networks: A unified framework

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 6, 2005, Pages 655-667

  Sridhara, Srinivasa R ^a   Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Bus coding; Bus delay; Crosstalk avoidance; Interconnection networks; Low power; On chip buses; Reliability; System on chip

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; ELECTRIC POTENTIAL; ERROR DETECTION; INTERCONNECTION NETWORKS; RELIABILITY; SEMICONDUCTOR MATERIALS; SIGNALING;

BUS CODING; BUS DELAYS; CROSSTALK AVOIDANCE; LOW-POWER; ON-CHIP BUSES; SYSTEM-ON-CHIP;

SIGNAL ENCODING;

EID: 23744468720     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.848816     Document Type: Article

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