A new kind of processor interface for a system-on-a-chip processor with TIE ports and TIE queues of Xtensa LX

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2005, Issue , 2005, Pages 72-79

  Tohara, Tomonari ^a  

^a Tensilica Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; CONGESTION CONTROL (COMMUNICATION); INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); THROUGHPUT;

COMMUNICATION BOTTLENECK; PROCESSOR INTERFACE ARCHITECTURE; SYSTEM-ON-A-CHIP (SOC);

MULTIPROCESSING SYSTEMS;

EID: 33847006556     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2005.23     Document Type: Conference Paper

References (12)

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