Packetization and routing analysis of on-chip multiprocessor networks

Journal of Systems Architecture

Volumn 50, Issue 2-3, 2004, Pages 81-104

  Ye, Terry Tao ^a   Benini, Luca ^b   De Micheli, Giovanni ^a  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Networks on chip; On chip communication; On chip multiprocessors; On chip networks

Indexed keywords

BENCHMARKING; CONSTRAINT THEORY; ENERGY UTILIZATION; NETWORK PROTOCOLS; PACKET NETWORKS; PARALLEL PROCESSING SYSTEMS; RESOURCE ALLOCATION; VLSI CIRCUITS;

ON-CHIP COMMUNICATION; ON-CHIP MULTIPROCESSORS; PACKETIZATION;

INTERCONNECTION NETWORKS;

EID: 1242309793     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2003.07.005     Document Type: Article

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