Efficient On-Chip Global Interconnects

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 271-274

  Ho, Ron ^a   Mai, Ken ^a   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; ELECTRIC POTENTIAL;

GLOBAL INTERCONNECTS;

MICROPROCESSOR CHIPS;

EID: 0141538149     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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3. E. Waingold et al., "Baring it all to software: Raw machines," IEEE Computer, September 1997, pp. 86-93.
4. K. Mai et al., "Smart Memories: A Modular Reconfigurable Architecture," Proc. ISCA, June 2000, pp. 161-71.
5. W. Dally et al., "A Single-Chip Terabit Switch," Hot Chips 13, 2001.
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7. B. Nikolic et al., "Improved Sense Amplifier-Based Flip-Flop: Design and Measurements," IEEE JSSC, June 2000, pp. 876-84.
8. C. Svensson, "Optimum Voltage Swing on On-Chip and Off-Chip Interconnect," IEEE JSSC, July 2001, pp. 1108-12.
9. R. Ho et al., "Applications on On-Chip Samplers for Test and Measurement of Integrated Circuits," Symp. VLSI Circuits, June 1998, pp. 138-9.