Power constrained design of multiprocessor interconnection networks

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 408-416

  Patel, Chirag S ^a   Chai, Sek M ^a   Yalamanchili, Sudhakar ^a   Schimmel, David E ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS;

ORTHOGONAL MULTIPROCESSOR INTERCONNECTION NETWORKS; POWER CONSTRAINED DESIGN;

INTERCONNECTION NETWORKS;

EID: 0031373275     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)