Key research problems in NoC design: A holistic perspective

CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2005, Pages 69-74

  Ogras, Umit Y ^a   Hu, Jingcao ^a   Marculescu, Radu ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Multi processor systems; Networks on Chip; Systems on Chip

Indexed keywords

COMPUTER ARCHITECTURE; MULTIPROCESSING SYSTEMS; OPTIMIZATION; PROBLEM SOLVING;

NETWORKS-ON-CHIP; SYSTEMS-ON-CHIP;

MICROPROCESSOR CHIPS;

EID: 27644494723     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (38)

1. A. Jantsch, H. Tenhunen (Eds.). Networks-on-Chip. Kluwer, 2003.
2. S. Kumar, et. al. Network on a chip: An architecture for billion transistor era. In Proc. IEEE NorChip Conf, 2000.
3. W. Dally, B. Towles. Route packets, not wires: On-chip interconnection networks. In Proc. of DAC, June 2001.
4. L. Benini, G. De Micheli. Networks on chips: A new SoC paradigm. IEEE Computer. 35(1), 2002.
5. J. Henkel, et. al. On-chip networks: A scalable communication-centric embedded system design paradigm. In Proc. VLSI Design 2004.
6. J. Hu, R. Marculescu. Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. on CAD of Integrated Circuits and Systems, 24(4), April 2005.
7. S. Murali, G. De Micheli. Bandwidth-constrained mapping of cores onto NoC architectures. In Proc. DATE, 2004.
8. W. Hung, et. al. Thermal-aware IP virtualization and placement for Networks-on-Chip architecture. In Proc. ICCD, 2004.
9. G. Ascia et. al. Multi-objective mapping for mesh-based NoC architectures. In Proc. CODES, 2004
10. A. Jalabert, et. al. xpipesCompiler: A tool for instantiating application specific Networks on Chip. In Proc. DATE, 2004.
11. S. Murali, G. De Micheli. SUNMAP: A tool for automatic topology selection and generation for NoCs. In Proc. DAC, 2004.
12. M. Kreutz, et. al. Communication architectures for System-On-Chip. Symp. on Integrated Circuits and Systems Design, 2001.
13. A. Pinto, et. al. Efficient synthesis of networks on chip. In Proc. ICCD, Oct. 2003.
14. K. Srinivasan, et. al. Linear programming based techniques for synthesis of Network-on-Chip architectures. In Proc. ICCD, 2004.
15. U. Y. Ogras, R. Marculescu. Energy- and performance- driven customized architecture synthesis using a decomposition approach. In Proc. DATE, 2005.
16. J. Duato, et. al.Interconnection Networks: An Engineering Approach. Morgan Kaufmann, 2002.
17. C. J. Glass, L. M. Ni. The turn model for adaptive routing. In Proc. ISCA, May 1992.
18. J. Hu, R. Marculescu. DyAD-Smart routing for Networks-on-Chip. In Proc. DAC, June 2004.
19. L. Shang et. al. PowerHerd: Dynamically satisfying peak power constraints in interconnection networks. In Proc. Intl. Symp. on Supercomputing, June 2003.
20. T. Dumitras, R. Marculescu. On-Chip stochastic communication. In Proc. DATE, March 2003.
21. M. Pirretti et. al. Fault tolerant algorithms for Network-On-Chip interconnect. In Proc. IEEE Symp. on VLSI, February 2004
22. I. Saastamoinen, el. al. Buffer implementation for Proteo Network-on-Chip. In Proc. Intl. Symp. on Circuits and Systems, 2003.
23. V. Chandra, et. al. An interconnect channel design for high performance integrated circuits. In Proc. DATE, Feb. 2004.
24. J. Hu, R. Marculescu. Application-specific buffer space allocation for Networks-on-Chip router design. In Proc. ICCAD, 2004.
25. T. Lin, L. T. Pileggi. Throughput-driven IC communication fabric synthesis. In Proc. ICCAD 2002.
26. J. Liang, el. al. An architecture and compiler for scalable on-chip communication. IEEE Trans. on VLSI Systems, 12(7), July 2004.
27. J. Hu, R. Marculescu. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In Proc. DATE, 2004.
28. Y. Xie, W. Wolf. Allocation and scheduling of conditional task graph in hardware/software co-synthesis. In Proc. DATE 2001.
29. G. Varatkar, R. Marculescu. On-chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Trans. on VLSI, 12(1), 2004.
30. http://cares.icsl.ucla.edu/MediaBench/applications.html
31. E. Bolotin, et. al. QoS architecture and design process for Networks-on-Chip. Journal of Systems Arch., vol. 50, 2004.
32. T. Bjerregaard, J. Sparso. A Router architecture for connection-oriented service guarantees in the MANGO clockless Network-on-Chip, In. Proc, DATE, 2005.
33. J. Dielissen, et. al. Concepts and implementation of the Philips Network-on-Chip. IP-based SoC Design, Nov. 2003.
34. M. Millberg, et. al. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In Proc. DATE, 2004.
35. K. Lee, et. al. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform. Intl. Solid-State Circuits Conf., 2004.
36. L. P.Carloni, et. al. Theory of latency-insensitive design. IEEE Trans. on CAD of, Integrated Circuits and Systems, 20(9), Sept. 2001.
37. T. T. Ye, G-De Micheli. Physical planning for multiprocessor networks and switch fabrics. In Proc. ASAP, 2003.
38. A. Morgenshtein, et. al. Comparative analysis of serial vs. parallel links in networks on chip. Intl. Symp. on System-on-Chip 2004.