Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Integration, the VLSI Journal

Volumn 38, Issue 3, 2005, Pages 353-382

  Vellanki, Praveen ^a   Banerjee, Nilanjan ^a   Chatha, Karam S ^a,b  

^a ARIZONA STATE UNIVERSITY   (United States)

^b Arizona State University   (United States)

Author keywords

Error control; Network on chip; Performance; Power consumption; Quality of service

Indexed keywords

CROSSTALK; DATA REDUCTION; INFORMATION ANALYSIS; JITTER; PACKET NETWORKS; QUALITY OF SERVICE; ROUTERS; TELECOMMUNICATION TRAFFIC;

ERROR CONTROL; NETWORK-ON-CHIP; POWER CONSUMPTION; QUALITY-OF-SERVICE;

MICROPROCESSOR CHIPS;

EID: 10444240445     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2004.07.009     Document Type: Article

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