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Volumn 2003-January, Issue , 2003, Pages 225-232

Towards on-chip fault-tolerant communication

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DESIGN; DISTRIBUTED COMPUTER SYSTEMS; FAULT TOLERANCE; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; STOCHASTIC MODELS; STOCHASTIC SYSTEMS; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS;

EID: 84954417739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195021     Document Type: Conference Paper
Times cited : (130)

References (17)
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    • W. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In Proc. DAC, June 2001.
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  • 8
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    • IC design in high-cost nanometer technologies era
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    • W. Maly. IC design in high-cost nanometer technologies era. In Proc. DAC, June 2001.
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    • Maly, W.1
  • 12
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    • G. Martin. Design methodologies for system level IP. In Proc. DATE, pages 286-289, March 1998.
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    • Martin, G.1
  • 13
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    • On spreading a rumor
    • B. Pittel. On spreading a rumor. SIAM Journal of Appl. Math., 47(3):213-223, 1987.
    • (1987) SIAM Journal of Appl. Math. , vol.47 , Issue.3 , pp. 213-223
    • Pittel, B.1
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    • CMOS scaling into the nanometer regime
    • April
    • Y. Taur and et. al. CMOS scaling into the nanometer regime. In Proc. of the IEEE, volume 85, April 1997.
    • (1997) Proc. of the IEEE , vol.85
    • Taur, Y.1
  • 17
    • 2442489756 scopus 로고    scopus 로고
    • Interconnection of autonomous error-tolerant cells
    • T. Valtonen et. al. Interconnection of autonomous error-tolerant cells. In Proc. ISCAS, 2002.
    • (2002) Proc. ISCAS
    • Valtonen, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.