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Volumn 25, Issue 2, 2005, Pages 21-29

Niagara: A 32-way multithreaded sparc processor

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CACHE MEMORY; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; PIPELINE PROCESSING SYSTEMS; SERVERS;

EID: 20344374162     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.35     Document Type: Article
Times cited : (670)

References (7)
  • 1
    • 0034312339 scopus 로고    scopus 로고
    • "A Performance Methodology for Commercial Servers"
    • S.R. Kunkel et al., "A Performance Methodology for Commercial Servers," IBM J. Research and Development, vol. 44, no 6, 2000, pp. 851-872.
    • (2000) IBM J. Research and Development , vol.44 , Issue.6 , pp. 851-872
    • Kunkel, S.R.1
  • 2
    • 0037619265 scopus 로고    scopus 로고
    • "Web Search for a Planet: The Architecture of the Google Cluster"
    • Mar.-Apr
    • L. Barroso, J. Dean, and U. Hoezle, "Web Search for a Planet: The Architecture of the Google Cluster," IEEE Micro, vol 23, no. 2, Mar.-Apr. 2003, pp. 22-28.
    • (2003) IEEE Micro , vol.23 , Issue.2 , pp. 22-28
    • Barroso, L.1    Dean, J.2    Hoezle, U.3
  • 3
    • 2842571467 scopus 로고    scopus 로고
    • "The Case for a Single Chip Multiprocessor"
    • Proc. 7th Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS VII)
    • K. Olukotun et al., "The Case for a Single Chip Multiprocessor," Proc. 7th Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS VII), 1996, pp. 2-11.
    • (1996) , pp. 2-11
    • Olukotun, K.1
  • 4
    • 84976738400 scopus 로고
    • "Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations"
    • Proc. 6th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS VI) ACM Press
    • J. Laudon, A. Gupta, and M. Horowitz, "Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations," Proc. 6th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS VI) ACM Press, 1994, pp. 308-316.
    • (1994) , pp. 308-316
    • Laudon, J.1    Gupta, A.2    Horowitz, M.3
  • 5
    • 0033722744 scopus 로고    scopus 로고
    • "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing"
    • Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA 00), IEEE CS Press
    • L. Barroso et al., "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA 00), IEEE CS Press, 2000, pp. 282-293.
    • (2000) , pp. 282-293
    • Barroso, L.1
  • 6
    • 3042627210 scopus 로고    scopus 로고
    • "A Chip Multithreaded Processor for Network-Facing Workloads"
    • Mar.-Apr
    • S. Kapil, H. McGhan, and J. Lawrendra, "A Chip Multithreaded Processor for Network-Facing Workloads," IEEE Micro, vol. 24, no. 2, Mar.-Apr. 2004, pp. 20-30.
    • (2004) IEEE Micro , vol.24 , Issue.2 , pp. 20-30
    • Kapil, S.1    McGhan, H.2    Lawrendra, J.3
  • 7
    • 28144440657 scopus 로고    scopus 로고
    • "Implementation of a 4th-Generation 1.8 GHz Dual Core Sparc V9 Microprocessor"
    • Proc. Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press
    • J. Hart et al., "Implementation of a 4th-Generation 1.8 GHz Dual Core Sparc V9 Microprocessor," Proc. Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press, 2005, http://www.isscc.org/isscc/2005/ ap/ISSCC2005AdvanceProgram.pdf.
    • (2005)
    • Hart, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.