A coding framework for low-power address and data busses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 2, 1999, Pages 212-221

  Ramprasad, Sumant ^b   Shanbhag, Naresh R ^a,b   Hajj, Ibrahim N ^a,b  

^a IEEE

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

CMOS VLSI; Coding; High capacitance busses; Low power design; Switching activity

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DECODING; ENCODING (SYMBOLS);

ADDRESS BUSSES; DATA BUSSES; SOURCE CODING;

VLSI CIRCUITS;

EID: 0032628047     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.766748     Document Type: Article

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