Æthereal network on chip: Concepts, architectures, and implementations

IEEE Design and Test of Computers

Volumn 22, Issue 5, 2005, Pages 414-421

  Goossens, Kees ^a   Dielissen, John ^a   Rǎdulescu, Andrei ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; INTERFACES (COMPUTER); MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; ROUTERS;

CENTRALIZED PROGRAMMING MODEL; DISTRIBUTED PROGRAMMING MODEL; NETWORKS ON CHIPS;

COMPUTER NETWORKS;

EID: 27344456043     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.99     Document Type: Article

References (12)

1. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computer, vol. 35, no. 1, Jan. 2002, pp. 70-80.
2. K. Goossens et al., "A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification," Proc. Design, Automation and Test in Europe (DATE 05), IEEE CS Press, 2005, pp. 1182-1187.
3. E. Rijpkema et al., "Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip," Proc. IEE Computers and Digital Techniques, IEEE Press, 2003, vol. 150, no. 5, pp. 294-302.
4. A. Rǎdulescu et al., "An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, Jan. 2005, pp. 4-17.
5. T. Bjerregaard and J. Sparso, "A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip," Proc. Design, Automation and Test in Europe (DATE 05), IEEE CS Press, 2005, pp. 1226-1231.
6. M. Millberg et al., "Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip," Proc. Design, Automation and Test in Europe (DATE 04), IEEE CS Press, 2004, pp. 20890-20895.
7. J. Rexford, "Tailoring Router Architectures to Performance Requirements in Cut-Through Networks," PhD thesis. Dept. Computer Science and Eng., Univ. of Michigan, 1999.
8. H. Zhang, "Service Disciplines for Guaranteed Performance Service in Packet-Switching Networks," Proc. IEEE, IEEE Press, 1995, pp. 1374-1396.
9. A. Edman and C. Svensson, "Timing Closure through a Globally Synchronous, Timing Partitioned Design Methodology," Proc. 41st Design Automation Conf. (DAC 04), IEEE CS Press, 2004, pp. 71-74.
10. E. Rijpkema et al., "A Router Architecture for Networks on Silicon," Proc. Workshop on Embedded Systems, 2001; http://www. homepages.inf.ed.ac.uk/kgoossen/2001-progress.pdf.
11. E. Lee and D. Messerschmitt, "Synchronous Data Flow," Proc. IEEE, IEEE Press, 1987, pp. 1235-1245.
12. ATM Forum, ATM User-Network Interface Specification, Prentice Hall, 1994.