Razor: Circuit-level correction of timing errors for low-power operation

IEEE Micro

Volumn 24, Issue 6, 2004, Pages 10-20

  Ernst, Dan ^a,d   Das, Shidhartha ^a   Lee, Seokwoo ^a   Blaauw, David ^a   Austin, Todd ^a   Mudge, Trevor ^a   Kim, Nam Sung ^b   Flautner, Krisztiéan ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b INTEL CORPORATION   (United States)

^c ARM LTD   (United Kingdom)

^d UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; ERROR ANALYSIS; ERROR CORRECTION; ERROR DETECTION; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; LOGIC GATES; MULTIPLYING CIRCUITS; VOLTAGE CONTROL;

DYNAMIC VOLTAGE SCALING; RAZOR ERROR CORRECTION; RAZOR ERROR DETECTION; RAZOR FLIP FLOP;

MICROPROCESSOR CHIPS;

EID: 15044339297     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.85     Document Type: Article

References (10)

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