SUNMAP: A tool for automatic topology selection and generation for NoCs

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 914-919

  Murali, Srinivasan ^a   De Micheli, Giovanni ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Mapping; Networks on Chip; SystemC; Systems On Chip; Topology

Indexed keywords

COMMUNICATION DELAY; NETWORKS ON CHIP (NOC); SYSTEM ON CHIP (SOC); SYSTEMSC;

AUTOMATION; COMPUTER NETWORKS; COMPUTER SIMULATION; COMPUTER SYSTEMS; ENERGY DISSIPATION; LOGIC DESIGN; MAPPING; PROGRAM PROCESSORS; TOPOLOGY;

COMMUNICATION SYSTEMS;

EID: 4444335188     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2004.239780     Document Type: Conference Paper

References (23)

1. M. Sgroi et al., " Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design", in Proc. Design Automation Conference, 2001.
2. L.Benini and G.De Micheli, "Networks on Chips: A New SoC Paradigm", IEEE Computers, pp. 70-78, Jan. 2002.
3. P.Guerrier, A.Greiner, "A generic architecture for on-chip packet switched interconnections", DATE 2000, pp. 250-256, March 2000.
4. S.Kumar et al., "A network on chip architecture and design methodology", ISVLSI 2002, pp.105-112, 2002.
5. E.Rijpkema et al., "Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip",DATE 2003, pp. 350-355, Mar 2003.
6. F.Karim et al., "On-chip communication architecture for OC-768 network processors", Design Automation Conference, June 2001.
7. X.Zhu, S.Malik, "A Hierarchical Modeling Framework for On-Chip Communication Architectures", ICCD 2002, pp. 663-671, Nov 2002.
8. L. Jian, et. al, "aSOC: A Scalable, Single-Chip communications Architecture", PACT 2000, Oct. 2000, pp. 37-46.
9. D.Siguenza-Tortosa, J. Nurmi, " Proteo: A New Approach to Network-on-Chip", in CSN 02, Sep. 2002.
10. S.J.Lee et al.," An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip", ISSCC 2003, Feb. 2003.
11. A.Jantsch, H.Tenhunen, "Networks on Chip", Kluwer Academic Publishers, 2003.
12. S.J.Krolikoski, et. al, "Methodology and Technology for Virtual Component Driven Hardware/Software Co-Design on the System-Level", ISCAS 99, pp. 456-459, June 1999.
13. E.B.Van der Tol, E.G.T.Jaspers,"Mapping of MPEG-4 Decoding on a Flexible Architecture Platform", SPIE 2002, pp. 1-13, Jan, 2002.
14. A.Pinto et. al, "Efficient Synthesis of Networks on Chip", ICCD 2003, pp. 146-150, Oct 2003.
15. W.H.Ho, T.M.Pinkston, "A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns", HPCA 2003, pp. 377-388, Feb 2003.
16. J.Hu, R.Marculescu, "Energy-Aware Mapping for Tile-based NOC Architectures Under Performance Constraints", ASP-DAC 2003, Jan 2003.
17. "×pipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs", pp. 536-539, ICCD, 2003.
18. "×pipesCompiler: A Tool For Instantiating Application Specific Networks on Chips", Vol. 2, pp. 20884, DATE 2004.
19. "Bandwidth Constrained Mapping of Cores onto NoC Architectures", Vol. 2, pp. 20896, DATE 2004.
20. J.G.Kim, Y.D.Kim, "A linear programming-based algorithm for floorplanning in VLSI design ", IEEE Transactions on CAD, pp. 584 -592, Vol. 22, Issue: 5, May 2003,
21. N. Sherwani, "Algorithms for VLSI Physical Design Automation". Kluwer Academic Publishers, 1995.
22. H.S Wang et al., "Orion: A Power-Performance Simulator for Interconnection Networks", MICRO, Nov. 2002.
23. R. Ho, K. Mai, and M. Horowitz, "The Future of Wires", Proceedings of the IEEE, pp. 490-504, April 2001.