QNoC: QoS architecture and design process for network on chip

Journal of Systems Architecture

Volumn 50, Issue 2-3, 2004, Pages 105-128

  Bolotin, Evgeny ^a   Cidon, Israel ^a   Ginosar, Ran ^a   Kolodny, Avinoam ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Network on chip; QNoC; QNoC design process; QoS architecture; Wormhole switching

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; NETWORK PROTOCOLS; QUALITY OF SERVICE; ROUTERS; SIGNAL PROCESSING; SWITCHING CIRCUITS; TELECOMMUNICATION TRAFFIC; THROUGHPUT;

INTER-MODULE CONTROL SIGNALS; NETWORKS-ON-CHIP (NOC); WORMHOLE SWITCHING;

MICROPROCESSOR CHIPS;

EID: 1242309790     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2003.07.004     Document Type: Article

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