A 160mW, 80nA standby, MPEG-4 audiovisual LSI with 16Mb embedded DRAM and a 5GOPS adaptive post filter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Arakida, Hideho ^a   Takahashi, Masafumi ^a   Tsuboi, Yoshiro ^a   Nishikawa, Tsuyoshi ^a   Yamamoto, Hideaki ^a   Fujiyoshi, Toshihide ^a   Kitasho, Yoshiyuki ^a   Ueda, Yasuyuki ^a   Watanabe, Manabu ^a   Fujita, Tetsuya ^a   Terazawa, Toshihiro ^a   Ohmori, Kenji ^a   Koana, Masahiro ^a   Nakamura, Hiroki ^a   Watanabe, Eiichi ^a   Ando, Hirofumi ^a   Aikawa, Takeshi ^a   Furuyama, Tohru ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE FILTERING; ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; DIGITAL STORAGE; DYNAMIC RANDOM ACCESS STORAGE; IMAGE CODING; LEAKAGE CURRENTS; MOTION COMPENSATION; MOTION ESTIMATION; MULTIMEDIA SYSTEMS; VECTOR QUANTIZATION;

ADAPTIVE POST FILTER; DIRECT MEMORY ACCESS CONTROLLER; MOVING PICTURE EXPERTS GROUP; POST FILTERING ENGINE;

LSI CIRCUITS;

EID: 0037631147     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Nishikawa, T., et al., "A 60MHz 240mW MPEG-4 Video-Phone LSI with 16Mb Embedded DRAM," ISSCC Digest of Technical Papers, pp.230-231, 2000.
2. Hashimoto, T.,. et al., "A 90mW MPEG4 Video Codec LSI with the Capability for Core Profile," ISSCC Digest of Technical Papers, pp.140-141, 2001.
3. Yoon, C.-W. et al., "A 80/20MHz 160mW Multimedia Processor integrated with Embedded DRAM MPEG-4 Accelerator and 3D Rendering Engine for Mobile Applications," ISSCC Digest of Technical Papers, pp. 110-111, 2001.
4. Ohashi, M., et al., "A 27MHz 11.1mW MPEG-4 Video Decoder LSI for Mobile Application," ISSCC Digest of Technical Papers, pp.366-367, 2002.