Communication scheduling

SIGPLAN Notices (ACM Special Interest Group on Programming Languages)

Volumn 35, Issue 11, 2000, Pages 82-92

  Mattson, Peter ^a   Dally, William J ^a   Rixner, Scott ^a   Kapasi, Ujval J ^a   Owens, John D ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 17544363191     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/356989.356997     Document Type: Article

References (17)

1. Capitanio, A., Dutt, N., and Nicolau, A. "Partitioned register files for VLIWs: A preliminary analysis of trade-offs." Proceedings of the 25th Annual International Symposium on Microarchitecture, Dec., 1992, pp. 292-300.
2. Colwell, R., Hall, W., Joshi, C., Papworth, D., Rodman, P., and Tornes, J. "Architecture and implementation of a VLIW supercomputer." Proceedings in Supercomputing, Nov., 1990, pp. 910-919.
3. Dehnert, J. and Towle, R. "Compiling for the Cydra 5." Journal of Supercomputing, Jan., 1993, 182-227.
4. Desoli, G. "Instruction assignment for clustered VLIW DSP compilers: A new approach." Technical Report HPL-98-13, Hewlett-Packard Laboratories, Feb., 1998.
5. Diefendorff, K. and Dubey, P. "How multimedia workloads will change processor design." Computer, Sept., 1997, pp. 43-45.
6. Ellis, J., Bulldog: A compiler for VLIW architectures. Cambridge, MA: MIT Press, 1986.
7. Fernandes, M., Llosa, J., and Topham, N., "Distributed modulo scheduling." Proceedings of the 5th Annual International Conference on High Performance Computer Architecture, Jan., 1999, pp. 130-134.
8. Grossman, J. and Dally, W. "Point sample rendering." Proceedings of the 9th Eurographics Workshop on Rendering, June, 1998, pp. 181-192.
9. Lam, M. "Software pipelining: An effective scheduling technique for VLIW machines." Proceedings of the Conference on Programming Language Design and Implementation, June, 1988, pp. 318-328.
10. Lowney, P., Freudenberger, S., Karzes, T., Lichtenstein, W., Nix, R., O'Donnell, J., and Ruttenberg, J. "The Multiflow trace scheduling compiler." Journal of Supercomputing, Jan., 1993, pp. 51-142.
11. Mangione-Smith, W., Abraham, S., and Davidson, E. "Register requirements of pipelined processors." Proceedings of the International Conference on Supercomputing, July, 1992, pp. 260-271.
12. Nystrom, E., and Eichenberger, A. "Effective cluster assignment for modulo scheduling." Proceedings of the 31st Annual International Symposium on Microarchitecture, Dec., 1998, pp. 103-114.
13. Ozer, E., Banerjia, S., and Conte, T. "Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures." Proceedings of the 31st Annual International Symposium on Microarchitecture, Dec., 1998, pp. 308-315.
14. Rau, B., Glaeser, C., and Picard, R., "Efficient code generation for horizontal architectures: Compiler techniques and architectural support." Proceedings of the International Symposium on Computer Architecture, July, 1982, pp. 131-139.
15. Rixner, S., Dally, W. J., Khailany, B., Mattson, P., Kapasi, U. J., and Owens, J. D. "Register organization for media processing", 6th International Symposium on High-performance Computer Architecture, Jan., 2000, pp. 375-386.
16. Rixner, S., Dally, W. J., Kapasi, U. J., Khailany, B., Lopez-Lagunas, A., Mattson, P., and Owens, J. D. "A bandwidth-efficient architecture for media processing", Proceedings of the 31st Annual International Symposium on Microarchitecture, Dec., 1998, pp. 3-13.
17. Stolzer, E. and Leiss, E., "Modulo scheduling for the TMS320C6x VLIW DSP architecture," Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, May, 1999, pp. 28-34.