A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1226-1231

  Bjerregaard, Tobias ^a   Sparsø, Jens ^a  

^a TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; ROUTERS;

CONNECTION-ORIENTED SERVICE; ROUTER ARCHITECTURE;

SYSTEMS ANALYSIS;

EID: 27344444925     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.36     Document Type: Conference Paper

References (18)

1. International technology roadmap for semiconductors (ITRS) 2001. Technical report, International Technology Roadmap for Semiconductors, 2001.
2. Open Core Protocol Specifi cation. Release 2.0, 2003.
3. W. Bainbridge and S. Furber. Delay insensitive system-on-chip interconnect using 1-of-4 data encoding. In Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems, pages 118- 126, March 2001.
4. L. Benini and G. D. Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70-78, January 2002.
5. T. Bjerregaard and J. Sparsø. Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip. In Proceedings of the IEEE Norchip Conference, 2004.
6. T. Bjerregaard and J. Sparsø. A scheduling discipline for latency and bandwidth guarantees in asynchronous networkon-chip. In Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE, 2005.
7. W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th Design Automation Conference, pages 684-689. June 2001.
8. J. Dielissen, A. Radulescu, K. Goossens, and E. Rijpkema. Concepts and implementation of the phillips network-on-chip. In Proceedings of the IPSOC'03, 2003.
9. T. Felicijan and S. B. Furber. An asynchronous on-chip network router with quality-of-service (QoS) support. In Proceedings IEEE International SOC Conference, pages 274-277. IEEE, 2004.
10. A. Jantsch and H. Tenhunen. Networks on Chip. Kluwer Academic Publishers, 2003.
11. M. MillBerg, E. Nilsson, R. Thid, and A. Jantsch. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In Proceedings of the Design, Automation and Testing in Europe Conference (DATE'04). IEEE, 2004.
12. R. Mullins, A. West, and S. Moore. Low-latency virtual-channel routers for on-chip networks. In Proceedings of the International Symposium on Computer Architecture (ISCA) 2004. IEEE, 2004.
13. J. Muttersbach, T. Villiger, K. Kaeslin, N. Felber, and W. Fichtner. Globally-Asynchronous Eocally-Synchronous Architectures to Simplify the Design of On-CHIP Systems. In Proc. 12th International ASIC/SOC Conference, pages 317-321, Sept. 1999.
14. S. F. Nielsen and J. Sparsø. Analysis of low-power SoC interconnection networks. In Proceedings of Nordchip 2001. pages 77-86, 2001.
15. L.-S. Peh and W. J. Dally. A delay model for router microarchitectures. IEEE Micro, 21:26-34, 2001.
16. E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. V. Meerbergen, P. Wielage, and E. Waterlander. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. In Proceedings of the Design, Automation and Test in Europe Conference (DATE'03), pages 350-355. IEEE, 2003.
17. J. Sparsø and S. Furber. Principles of Asynchronous Circuit Design - a Systems Perspective. Kluwer Academic Publishers, Boston, 2001.
18. D. Sylvester and K. Keutzer. A global wiring paradigm for deep submicron design. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 19:242-252, 2000.