Scalar operand networks

IEEE Transactions on Parallel and Distributed Systems

Volumn 16, Issue 2, 2005, Pages 145-162

  Taylor, Michael Bedford ^a   Lee, Walter ^a   Amarasinghe, Saman P ^a   Agarwal, Anant ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Distributed architectures; Interconnection architectures; Microprocessors

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; OPTIMIZATION; PROGRAM COMPILERS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

DISTRIBUTED ARCHITECTURES; INTERCONNECTION ARCHITECTURE; SCALAR OPERAND NETWORKS;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 14844348900     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2005.24     Document Type: Article

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