Fault tolerance overhead in network-on-chip flow control schemes

SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2005, Pages 224-229

  Pullini, Antonio ^a   Angiolini, Federico ^a   Bertozzi, Davide ^b   Benini, Luea ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b UNIVERSITY OF FERRARA   (Italy)

Author keywords

Error correction; Fault tolerance; Flow control; Network on chip

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; ERROR ANALYSIS; ERRORS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; FLOW CONTROL; INTEGRATED CIRCUITS; NETWORK ARCHITECTURE; QUALITY ASSURANCE; RELIABILITY; SYSTEMS ANALYSIS;

BUFFER MANAGEMENT; CHANNEL BANDWIDTHS; CONTROL MECHANISMS; CONTROL SCHEMES; FUNCTIONAL SIMULATIONS; NETWORK RESOURCES; NETWORK-ON-CHIP (NOC); NOC ARCHITECTURES; OPERATING MODES; PACKET PROPAGATION; RUNNING IN; SYSTEMS DESIGN; VIRTUAL PLATFORM (VIP);

NETWORK MANAGEMENT;

EID: 33847724870     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2005.4286861     Document Type: Conference Paper

References (22)

1. www.arm.com/products/solutions/AMBAAXI.html.
2. A.Radulescu, J.Dielissen, S.G.Pestana, O.P.Gangwal, E.Rijpkema, P.Wielage, and K.Goossens. An efficient on-chip ni offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24(1):4-17, 2005.
3. C.A.Zeferino and A.A.Susin. SoCIN: a parametric and scalable network-on-chip. In Symp. on Integrated Circuits and Systems Design, pages 169-174, September 2003.
4. C.A.Zeferino, F.G.M.E.Santo, and A.A.Susin. Paris: a parameterizable interconnect switch for networks-on-chip. In Symp. on Integrated Circuits and Systems Design, pages 204-209, September 2004.
5. C.A.Zeferino, M.E.Kreutz, L.Carro, and A.A.Susin. A study on communication issues for systems-on-chip. In Symp. on Integrated Circuits and Systems Design, pages 121-126, September 2002.
6. D.Bertozzi and L.Benini. xpipes: a network on chip architecture for gigascale systems-on-chip. IEEE Circuits and Systems Magazine, 4(2): 18-31, 2004.
7. D.Rostislav, V.Vishnyakov, E.Friedman, and R.Ginosar. An asynchronous router for multiple service levels networks. In Symp. on Integrated Circuits and Systems Design, pages 204 -209, March 2005.
8. D.Wiklund and D.Liu. Socbus: switched network on chip for hard real time embedded systems. In Int. Parallel and Distributed Processing Symposium, page 8pp, April 2003.
9. E.Nilsson, M.Millberg, J.Oberg, and A.Jantsch. Load distribution with the proximity congestion awareness in a network on chip. In DATE03, pages 1126-1127, 2003.
10. E.Rijpkema, K.Goossens, A.Radulescu, J.Dielissen, J. van Meerbergen, P.Wielage, and E.Waterlander. Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proc. on Computers and Digital Techniques, 150(5):294-302, 2003.
11. J.Chan and S.Parameswaran. Nocgen:a template based reuse methodology for networks on chip architecture. In Int. Conf. on VLSI Design, pages 717-720, 2004.
12. J.Liu, L. Zheng, and H.Tenhunen. A guaranteed-throughput switch for network-on-chip. In Int. Symp. on System-on-Chip, pages 31-34, November 2003.
13. K.Banerjee and A.Mehrotra. A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans. on Electron Devices, 49(11):2001-2007, 2002.
14. L.Benini and G. Micheli. Networks on chips: a new soc paradigm. IEEE Computer, 35(1):70-78, 2002.
15. M.Loghi, F.Angiolini, D.Bertozzi, L.Benini, and R.Zafalon. Analyzing on-chip communication in a MPSoC environment. In Proceedings of the IEEE Design and Test in Europe Conference (DATE), pages 752-757, February 2004.
16. M.Millberg, E.Nilsson, R.Thid, and A.Jantsch. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In DATE04, pages 890-895, February 2004.
17. M.Ruggiero, F.Angiolini, F.Poletti, D.Bertozzi, L.Benini, and R.Zafalon. Scalability analysis of evolving SoC interconnect protocols. In Int. Symp. on Systems-on-Chip, November 2004.
18. www.ocpip.org.
19. R.Tamhankar, S.Murali, and G. Micheli. Performance driven reliable link for networks on chip. In ASPDAC - Proceedings of the Asian Pacific Conference on Design Automation, 2005.
20. S.Khorsandi and A.L.Garcia. Robust non-probabilistic bounds for delay and throughput in credit-based flow control. In INFOCOMM, pages 577-584, 1996.
21. V.Chandra, A.Xu, H.Schmit, and L.Pileggi. An interconnect channel design methodology for high performance integrated circuits. In DATE04, pages 1138-1143, February 2004.
22. W.J.Dally and B.Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2004.