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Volumn , Issue , 1998, Pages 211-218
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Analysis, reduction and avoidance of crosstalk on VLSI chips
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Author keywords
[No Author keywords available]
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Indexed keywords
CROSSTALK;
ELECTRIC NETWORK ANALYSIS;
ELECTRIC WIRING;
VLSI CIRCUITS;
PATTERN DRIVEN ROUTING TOOLS;
TIMING CRITICALITY;
TIMING RELATIONSHIP;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0031683754
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (41)
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References (16)
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