Nanoscale CMOS

Proceedings of the IEEE

Volumn 87, Issue 4, 1999, Pages 537-570

  Wong, Hon Sum Philip ^a   Frank, David J ^a   Solomon, Paul M ^a   Wann, Clement H J ^a   Welser, Jeffrey J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DEVICES; MICROELECTRONICS; MOSFET DEVICES; NANOTECHNOLOGY; VLSI CIRCUITS;

DEVICE SCALING THEORY; MEMORY DEVICES; POWER CONSUMPTION;

CMOS INTEGRATED CIRCUITS;

EID: 0033115380     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.752515     Document Type: Article

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183. Hon-Sum Philip Wong (Senior Member, IEEE) received the B.Sc. (Hon.) degree from University of Hong Kong, Hong Kong, in 1982 and the Ph.D. degree in electrical engineering from Lehigh University, Bethlehem, PA, in 1988. He joined IBM T. J. Watson Research Center, Yorktown Heights, NY, in 1988 as a Research Staff Member. From 1988 to 1992, he worked on the design, fabrication, and characterization of a high-resolution, high color-fidelity CCD image scanner for art work archiving. Since 1993, he has been working on analysis, fabrication, and applications of nanoscale CMOS devices. His recent work included simulations of discrete random dopant fluctuation effects in small MOSFET's, the physics and technology of double-gate and back-gate MOSFET's, CMOS projection displays, and CMOS image sensors. David J. Frank (Member, IEEE) received the B.S. degree from the California Institute of Technology, Pasadena, in 1977 and the Ph.D. degree in physics from Harvard University, Cambridge, MA, in 1983. Since 1983, he has been employed at the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he is a Research Staff Member. His studies have included nonequilibrium superconductivity, modeling and measuring III-V devices, and exploring the limits of scaling of silicon technology. His recent work includes the modeling of innovative silicon devices, analysis of CMOS scaling issues, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and low-power circuit design. His interests include superconductor and semiconductor device physics, modeling and measurement, circuit design, and percolation in two-dimensional systems. Paul M. Solomon (Fellow, IEEE) was born Cape Town, South Africa. He received the B.Sc. degree in electrical engineering from the University of Cape Town, South Africa, in 1968 and the Ph.D. degree from the Technion, Haifa, Israel, in 1974 for work on the breakdown properties of silicon dioxide. Since 1975, he has been a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY. At IBM, his interests have been in the field of high-speed semiconductor devices. He has contributed to the theory of scaling bipolar transistors to very small dimensions and has developed methodologies to compare the performance of high-speed semiconductor devices. The design of high-speed semiconductor logic devices has been a continuing topic, ranging from self-aligned bipolar transistors through novel heterostructure field effect transistors and more recently to novel CMOS device concepts. He has contributed to the physics of transport in semiconductors and has taught the physics of high-speed devices at Stanford University. Dr. Solomon is a member of APS. Clement H. J. Wann received the B.S. degree from National Taiwan University in 1988 and the M.S. and Ph.D. degrees from University of California, Berkeley, in 1992 and 1996, respectively, all in electrical engineering. He joined IBM T. J. Watson Research Center, Yorktown Heights, NY, as a Research Staff Member in 1996. He is currently with IBM Semiconductor Research and Development Center, East Fishkill, NY. Jeffrey J. Welser (Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1988, 1989, and 1994, respectively. He has held short-term positions at Sumitomo Electric in Japan (1988) and at IBM T. J. Watson Research Center (1989-1990), Yorktown Heights, NY, working on GaAs devices, and a postdoctoral position at Stanford University (1995), where he continued his thesis research on SiGe materials and their applications to MOSFET devices. Since 1995, he has been a Research Staff Member at IBM T. J. Watson Research Center, and his current research activities focus on novel silicon devices, including vertical transistors and nanostructures, for a variety of memory applications.
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